Question 1 (Processes) a. A multi-programmed system with a single CPU has a very large number of CPU bound processes running on it that all have the same priority. Could you think of a CPU scheduling algorithm that would combine the lowest possible response times with the highest possible throughput and no starvation? Briefly explain your answer. b. Some operating systems force a context switch when a mutex (or spinlock) has been spin- ning for too long. List two reasons why this approach may be useful. c. This question relates to threads. Assume two user threads that increment a shared counter. The code runs on a multi-core system. Is it possible to obtain a concurrent implementation that is free of race conditions without using mutexes or semaphores (yes / no)? Briefly explain your answer. d. Figure 1 illustrates the times at which 10 different processes run on a single core of a single CPU. Every "row" represents a different process. The times increase towards the right, and processes with a higher priority are shown on top of the figure, processes with a lower

Question 1 (Processes) a. A multi-programmed system with a single CPU has a very large number of CPU bound processes running on it that all have the same priority. Could you think of a CPU scheduling algorithm that would combine the lowest possible response times with the highest possible throughput and no starvation? Briefly explain your answer. b. Some operating systems force a context switch when a mutex (or spinlock) has been spin- ning for too long. List two reasons why this approach may be useful. c. This question relates to threads. Assume two user threads that increment a shared counter. The code runs on a multi-core system. Is it possible to obtain a concurrent implementation that is free of race conditions without using mutexes or semaphores (yes / no)? Briefly explain your answer. d. Figure 1 illustrates the times at which 10 different processes run on a single core of a single CPU. Every "row" represents a different process. The times increase towards the right, and processes with a higher priority are shown on top of the figure, processes with a lower

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Description: Question 1 (Processes)a. A multi-programmed system with a single CPU has a very large number of CPU boundprocesses running on it that all have the same priority. Could you think of a CPU schedulingalgorithm that would combine the lowest possible res

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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a) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Suppose T1 does “Load X into register R1” machine instruction. Then the CPU scheduler switches the CPU to T2. Will T2 see the same vaue of R1 as loaded here by T1? (YES or NO)? Explain in less than 50 words. Be specific. (b) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Is it possible to have a moment (time instant) where both threads have made a request to Memory Unit to read some data (ex. as part of a “Load … into register …” instruction) and Memory Unit has not yet completed either of these two requests? Explain in less than 50 words.
Question) In a microprocessor-based system with several tasks that are supposed to be executed more or less simultaneously, there is a necessary condition for the sum of the computing times of the tasks. Please state this. b) The upper limit contained in this condition is limited in practice to about 35% for real-time systems. Why is, in general, so much overhead necessary to be real-time capable? Please name the main culprit for this.
Asymmetric and symmetric multiprocessing are also possible. Can you explain the pros and cons of utilising many CPUs in a same program?
Because of this, the CPU suspends any currently executing processes until the interrupt has been resolved. Interrupt service is the term used to describe this. What is the rationale for halting the procedure that is presently in progress? Isn't it possible, as an alternative, to just finish the presently operating operation and deal with the interruption afterward?
3) Assume we make an enhancement to computer that improves some mode of execution by afactor of 10. Enhanced mode is used 75% of the time, measured as percentage of executiontime when the enhanced mode is in use. What is the speedup we obtain from the fast mode?
8 The process of deciding which process should use the CPU is called as _______________ a. Planning b. Transmitting c. Scheduling d. Switching Just answer without explanation please
Assuming that two processes are currently running; delaying execution before one of the processes completes. For the most part, you may consider the phase 1 is the most essential and the other is less important. The main memory can store just one action at a time. The CPU explains how it performs calculation on that? The choices of both include the stages involved in the functioning of a CPU?
Problem: In a certain computer system, five (5) processes A, B, C, D, and E are active with their burst times (in ms) of 8, 10, 2, 4, and 3 respectively. These processes come at times (in ms.) 16, 0, 4, 20, and 29 respectively and use FCFS to schedule the execution. Required information: Draw the Gantt chart showing the execution of the CPU. What is the CPU utilization? What is the system’s throughput (in process /ms)?
b) Machine cycle defines a loop process with four major components. Explain why machine cycle is important? If the components of machine cycle are inter-swapped, would that cause any problems? Can we add another module to rectify the problem caused by inter-swapping? c) Cache memory and RAM both are based on transistor based then why cache memory is needed if we already have RAM (Random Access Memory) as a volatile memory? Is it possible to deploy any one type of memory in computer for all purposes?
If interrupt synchronization is turned off, it must be turned back on before leaving a critical section. For the sake of argument, let's say that one CPU disables interrupts as it reaches a critical section, while another CPU has its interrupt enable flag set to 0. P2 needs access to the crucial area and is willing to utilize any of the two CPUs available. Consider the consequences that are even somewhat feasible.
Questionnaire Having to Do with Computing Interprocess communication may become difficult to manage when both big-endian and little-endian CPU architectures are being used simultaneously. When will these issues ever be resolved?
What measures may be taken to ensure that a CPU's processing cycles are not needlessly squandered while it attempts to handle a huge number of instructions all at once? How reliant is the success of this plan's implementation on the availability of various resources? Explain how one of these impacts manifests itself.