Question 5: (Optional) Suppose you are using a RISC architecture where every step take one clock cycle to solve. You are using Pentium IV style that is 20 stage pipelines. Question, is if I have 30 instruction in program. a) How many cycles it will be taken to make pipeline full? b) What is total execution time? c) What is throughput?

Question 5: (Optional) Suppose you are using a RISC architecture where every step take one clock cycle to solve. You are using Pentium IV style that is 20 stage pipelines. Question, is if I have 30 instruction in program. a) How many cycles it will be taken to make pipeline full? b) What is total execution time? c) What is throughput?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing.
Suppose on a non-pipelined single-processor machine, you have the following breakdown: alu instructions make up 25% of the dynamic instruction count, and take 2 cycles to execute. Load/store instructions take 10 cycles to execute and make up 30% of the mix. Jumps take 4 cycles and make up 15%. All other instructions average 1.5 cycles. a. What is the average CPI? b. Suppose the architecture above is pipelined. If there are no stalls for any reason, what is the new CPI? c. If, for the architecture described in questions a and b, Load/store instructions generate 2 stalls on average, alu 0.2 stalls, and jumps cause 1 stall, what is the actual pipelined cpi?
Assume that registers $s0 and $s1 hold the values 0x80000000 and 0xD0000000, respectively. What is the value of $t0 for the following MIPS assembly code? Is the result in $t0 the desired result, or has there been overflow? add $t0, $s0, $s1 Is this overflow or underflow? Please explain
ANSWER THE QUSTIONS THAT IS WRITEN OR ON THE PICTURE PLEASE Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing. Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing. Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.
8. For a single cycle processor, the instruction breakdown of a program is listed as following. add 20% addi 20% not 0% beq 25% Iw SW 25% 10% What is the percentage of instructions that will use the output of sign extend circuit-module? a. b. What is sign extend circuit-module doing when its output is not needed for current instruction?
Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved?
2- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex. addi $t0, $Zero, -50 andi $t1, $t0, 7 Loop:and $t1,$t0,$t1 Sw $t0, 40 ($t1) Bne $t1,$ zero, Loop
What would be the clock period of a pipelined MIPS architecture with two stages, one comprising Instruction Fetch, Instruction Decode and Execute, the other one Memory and Write Back? Assume Memory and ALU take 2ns while Registers and other logic take Ins or less.
Please solve and show all work and steps. Thank you. For this question, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: add addi not beq lw sw 10% 15% 0% 30% 30% 15% In what fraction of all cycles is the data memory used? In what fraction of all cycles is the input of the sign-extend circuit needed?
1. Consider a pipelined RISC CPU with 11 stages. What is maximum speedup of this CPU over a non-pipelined implementation? 2. Given a 5-bit Global Branch History Buffer, how many Branch History Tables do we need?
Explain what you mean by "pipelining" in the context of improving processor speed, and then determine how many cycles it will take to run five instructions assuming each part of the machine requires one cycle. First, we'll look at the situation a) without pipelining and b) with pipelining. There are four ways to do this: a, b, c, and d, all of which include pipelining.
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?