Suppose on a non-pipelined single-processor machine, you have the following breakdown: alu instructions make up 25% of the dynamic instruction count, and take 2 cycles to execute. Load/store instructions take 10 cycles to execute and make up 30% of the mix. Jumps take 4 cycles and make up 15%. All other instructions average 1.5 cycles. a. What is the average CPI? b. Suppose the architecture above is pipelined. If there are no stalls for any reason, what is the new CPI? c. If, for the architecture described in questions a and b, Load/store instructions generate 2 stalls on average, alu 0.2 stalls, and jumps cause 1 stall, what is the actual pipelined cpi?

Suppose on a non-pipelined single-processor machine, you have the following breakdown: alu instructions make up 25% of the dynamic instruction count, and take 2 cycles to execute. Load/store instructions take 10 cycles to execute and make up 30% of the mix. Jumps take 4 cycles and make up 15%. All other instructions average 1.5 cycles. a. What is the average CPI? b. Suppose the architecture above is pipelined. If there are no stalls for any reason, what is the new CPI? c. If, for the architecture described in questions a and b, Load/store instructions generate 2 stalls on average, alu 0.2 stalls, and jumps cause 1 stall, what is the actual pipelined cpi?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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ANSWER THE QUSTIONS THAT IS WRITEN OR ON THE PICTURE PLEASE Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing. Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing. Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.
Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the Section I B of "Advanced Systems Concepts", i.e.:  a one clock cycle fetch  a two clock cycle decode  a three clock cycle execute and a 200 instruction sequence: Show your work. 7. o pipelining would require _____ clock cycles: 8. A scalar pipeline would require _____ clock cycles: How high is the increase in speed (percentage) compared to no pipelining? 9. A superscalar pipeline with two parallel units would require ______ clock cycles: How high is the increase in speed (percentage) compared to no pipelining?
Consider the two back to back instructions: lw $s1, 24($t3) add $t2, $s1, $t1 In the standard five stage, pipelined machine, consider the above two instructions where the second instruction tries to read a register that is being written to by the first instruction which is a 'load word' (lw) command. The scheduler has not done any juxtaposing of the commands. a. There will be no hazard situation as the load word deals with the data memory and the read is from the registers. b. There will be no hazard situation, since the read is from the same location where the write is taking place. c. It is possible to avoid a bubble in the flow by forwarding from the write back stage. d. It is not possible to avoid Data Hazard issues here and inserting a bubble is a way out of this issue.
The runtimes of the five stages of executing an instruction in a non-pipelined machine are listed below. Instruction Fetch 100ps Instruction Decode 200ps ALU 300ps Memory 300ps Write Back 200ps This is then converted into a pipelined machine M1 using the most critical stage as the cycle time. For a new machine M2, we are allowed to break up exactly one stage into two substages of equal times giving us a six stage pipeline. A1: Discuss in short clear sentences the latency differences between the machines M1 and M2. A2: Discuss in short clear sentences the throughput differences between the machines M1 and M2.
Consider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)
Examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? What is the total latency of an LW instruction in a pipelined and non-pipelined processor? If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? Assuming there are no stalls or hazards, what is the utilization of the data memory? Assuming there are no stalls or hazards, what is the utilization of the write-register port of the “Registers” unit? f. Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes…
What would be the clock period of a pipelined MIPS architecture with two stages, one comprising Instruction Fetch, Instruction Decode and Execute, the other one Memory and Write Back? Assume Memory and ALU take 2ns while Registers and other logic take Ins or less.
Consider the following portions of three different programs running at the same time on three processors in a symmetric multicore processor (SMP). Assume that before this code is run, Total is 15, val_1 is 45, val_2 is 25, and val_3 is 5. Core 1: Total = Total + val_1;Core 2: Total = Total - val_2;Core 3: Total = Total + val_3; 1. Show the assembly code for both instructions. Assume that Total, var_1, and var_2 are stored at 0x0100, 0x0120, and 0x0130 respectively.2. What are all the possible resulting values of Total? For each possibleoutcome, explain how we might arrive at those values. You will need to show all possible interleavings of instructions.3. How could you make the execution more deterministic so that only one set of values is possible?
Explain with an example how a 6 stage pipeline processor helps in speeding up the program execution as compared to non-pipelined processor. In the following example, find out the instruction pairs which can lead to data hazard in two stage pipeline and justify your answer. 1) MOV AL, 25H 2) MOV CH, 10H 3) MOV [2002H], AL 4) INC CH 5) MOV [2004H], CH 6) ADD DX, CH
Consider the following two SimpleRISC code snippets. Data hazards have to be handled in hardware. Let us consider two processors A and B: A supports only data interlocks, while B supports data interlocks and value forwarding. In each processor, in which cycle will the final instruction pass through the RW stage? Give the pipeline diagram in each case. (Assume the first instruction is in IF stage in cycle 1 in each case). (i) [1] st r3, 24[r1] [2] ld r4, 24[r1] (ii) [1] add r1, r1, r2 [2] sub r3, r1, r4 [3] add r4, r5, r6