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Question 8:  Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.

Question 8:  Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.

Systems Architecture
Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...
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Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing.

 

Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing.

 

Question 8:  Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.

Question 10: For the task graphs given in the figure determine the following: 1.Maximum degree of concurrency. 2.Critical path length. 3. Maximum achievable speedup over one process assuming that an arbitrarily large number of processes is available. 4. The minimum number of processes needed to obtain the maximum possible speedup. The maximum achievable speedup if the number of processes is limited to (a) 2, (b) 4, and (c) 8.
Transcribed Image Text:Question 10: For the task graphs given in the figure determine the following: 1.Maximum degree of concurrency. 2.Critical path length. 3. Maximum achievable speedup over one process assuming that an arbitrarily large number of processes is available. 4. The minimum number of processes needed to obtain the maximum possible speedup. The maximum achievable speedup if the number of processes is limited to (a) 2, (b) 4, and (c) 8.
Question 9: Consider the timing diagram of Figure 1. Assume that there is only a five-stage pipeline (fetch, read, encode, execute, and write). Redraw the diagram to show how many time units are now needed for ten instructions. Time 12 | 13 2 3 4 5 10 14 Instruction 1 FI DI co FOo EI wo Instruction 2 FI DI co FO EI wo Instruction 3 FI DI co FO EI WO Instruction 4 FI DI CO FO EI Instruction 5 FI DI co FO EI WO Instruction 6 FI DI CO FO EI wo Instruction 7 FI DI CO FO EI wo Instruction 8 FI DI CO FO EI WO Instruction 9 wo FI DI CO FO EI Figure 1: Timing Diagram for Instruction Pipeline Operation
Transcribed Image Text:Question 9: Consider the timing diagram of Figure 1. Assume that there is only a five-stage pipeline (fetch, read, encode, execute, and write). Redraw the diagram to show how many time units are now needed for ten instructions. Time 12 | 13 2 3 4 5 10 14 Instruction 1 FI DI co FOo EI wo Instruction 2 FI DI co FO EI wo Instruction 3 FI DI co FO EI WO Instruction 4 FI DI CO FO EI Instruction 5 FI DI co FO EI WO Instruction 6 FI DI CO FO EI wo Instruction 7 FI DI CO FO EI wo Instruction 8 FI DI CO FO EI WO Instruction 9 wo FI DI CO FO EI Figure 1: Timing Diagram for Instruction Pipeline Operation
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