R1 = X + 1 Y = R1 + R2 R1 = R2 + X Complete the following: Lay the instructions out as they would be fed through a 6-stage CPU pipeline not accounting for any hazards. S1: Fetch instruction, S2: Decode opcode, S3: Calc effective address of operands, S4: Fetch operands, S5: Execute instruction, S6: Store result Identify any hazards present "Fix" the pipeline process to remove the hazards

R1 = X + 1 Y = R1 + R2 R1 = R2 + X Complete the following: Lay the instructions out as they would be fed through a 6-stage CPU pipeline not accounting for any hazards. S1: Fetch instruction, S2: Decode opcode, S3: Calc effective address of operands, S4: Fetch operands, S5: Execute instruction, S6: Store result Identify any hazards present "Fix" the pipeline process to remove the hazards

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
A CPU has an instruction pipeline with the following 4 segments. 1.F1(Fetch Instruction) 2.DA(Decode, Address) 3.FO(Fetch Operand) 4.EX(Execution) D1: Add R1,R2 //R1=R1+R2 Add R4,R1 //R4=R4+R1 Add R4,R3 //R4=R4+R3 Cmp R4,R5 // compare R4 and R5 Jg D1 //if Jump Greater (if R4>R5) Sub R2,R1 //R2=R2-R1 Sub R2,R3 //R2=R2-R3 Jmp D1
1. T/F - if (B)=006000 (PC)=003600 (X)=000090, for the machine instruction 0x032026, the target address is 003000.2. T/F – PC register stores the return address for subroutine jump.3. T/F – S register contains a variety of information such as condition code.4. T/F – INPUT WORD 1034 – This means Operating system should reserve 1034 bytes in memory5. T/F - In a two pass assembler, adding literals to literal table and address resolution of local symbol are done using first pass and second pass respectively.
Consider the following instruction sequence where registers R1,R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. InstructionMOV R1,(5000)MOV R2,(R3)ADDR2,R1MOV (R3),R2INC R3DEC R1BNZ 1004HALTSemanticsR1←MEMORY[5000]R2←MEMORY[R3]R2←R1+R2MEMORY[R3]←R2R3←R3+1R1←R1−1Branch if not zero to thegiven absolute addressStopInstruction Size (bytes)44242221 Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 is
Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.
14. Consider the following assembly language instructions:mov al, 15mov ah, 15xor al, almov cl, 3shr ax, cladd al, 90Hadc ah, 0What is the value in ax register after execution of above instructions? a. 0270H b. 0170H c. 01E0H d. 0370H
Question 26 Assume that EBX and ECX have the following values EBX: FF FF FF 75 ECX: 00 00 01 A2 After the execution of the instruction SUB EBX, ECX The Value in EBX is _________ Group of answer choices 000001A2 00000000 FFFFFDD3 none of them Question 27 Assume that EBX and ECX have the following values EBX: FF FF FF 75 ECX: 00 00 01 A2 After the execution of the instruction MOV EBX, ECX The Value in ECX is _________ Group of answer choices 000001A2 FFFFFF75 00000000 none of them
The runtimes of the five stages of executing an instruction in a non-pipelined machine are listed below. Instruction Fetch 100ps Instruction Decode 200ps ALU 300ps Memory 300ps Write Back 200ps This is then converted into a pipelined machine M1 using the most critical stage as the cycle time. For a new machine M2, we are allowed to break up exactly one stage into two substages of equal times giving us a six stage pipeline. A1: Discuss in short clear sentences the latency differences between the machines M1 and M2. A2: Discuss in short clear sentences the throughput differences between the machines M1 and M2.
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory. Brief overview: opcode is 4 bits 14 different instructions implemented 8 general purpose registers RRR-type instructions are the largest, and take up 9 bits in register addresses 1 bit is a condition bit 2 bits unused simulated clock runs at a 10ns period or 100Mhz simulated memory is 512 bytes Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
The following sequence of instructions are executed in the basic 5-stage pipelined processor OR R1, R2, R3 OR R2, R1, R4 OR R1, R1, R2 a) Indicate the dependencies and their types b) Assume no forwarding in this pipelined processor indicate hazards and NOP instruction to eliminate them. c) Assume there is full forwarding, indicate hazards and NOP instructions to eliminate them