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Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD $TO, $T1, $T3 ADDI $51, $51, 4 LW $5e, 0($51) SUB $55, $50, $TO AND $T3, $T4, $55 Sw $55, 0($51) MULT $52, $56, $T3 SUB ȘT6, $T7, $6 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle).

Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD $TO, $T1, $T3 ADDI $51, $51, 4 LW $5e, 0($51) SUB $55, $50, $TO AND $T3, $T4, $55 Sw $55, 0($51) MULT $52, $56, $T3 SUB ȘT6, $T7, $6 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle).

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD $TO, $T1, $T3 ADDI $51, $s1, 4 LW $50, 0($s1) SUB $55, $e, $TO AND $T3, $T4, $55 SW $55, 0($51) MULT $52, $S6, ST3 SUB ST6, ȘT7, $6 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle).
Transcribed Image Text:Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD $TO, $T1, $T3 ADDI $51, $s1, 4 LW $50, 0($s1) SUB $55, $e, $TO AND $T3, $T4, $55 SW $55, 0($51) MULT $52, $S6, ST3 SUB ST6, ȘT7, $6 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle).
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