Sequential Circuit - Design an unsigned 3-bit counter using J-K flip-flops that increments by three on each clock cycle [Q(+1)=(Q+ + 3) % 8] while an external input E is set to 0 but increments by four on each clock cycle [Q(+1)=(Qt +4) % 8] while the external input E is set to 1. You need to show the truth table for the circuit and find a simplified expression for each output using a K-map. Show ALL of your work FQA QB • O 0 0 0 0 QB/QC/QA+1 QB+1|Qu+1|JA KA JB KB Jc Kc 1 0 0 20 0 1 30 40 0 1 - 1 0 1 - - 0-0-0-0-0-0-0 - 00-100 1 1 1 1 50 0 1 1 0 0 0 1 1 0 70 1 1 8 0 P 1 1 1 1 0 0 0 0 61 0 0 0 O 1 0 1 0 0 1 12 0 0 1 13 1 1 01 O 1 0 18 1 1 L 0 1 P 151 1 O 1 10000 о 0

Sequential Circuit - Design an unsigned 3-bit counter using J-K flip-flops that increments by three on each clock cycle [Q(+1)=(Q+ + 3) % 8] while an external input E is set to 0 but increments by four on each clock cycle [Q(+1)=(Qt +4) % 8] while the external input E is set to 1. You need to show the truth table for the circuit and find a simplified expression for each output using a K-map. Show ALL of your work FQA QB • O 0 0 0 0 QB/QC/QA+1 QB+1|Qu+1|JA KA JB KB Jc Kc 1 0 0 20 0 1 30 40 0 1 - 1 0 1 - - 0-0-0-0-0-0-0 - 00-100 1 1 1 1 50 0 1 1 0 0 0 1 1 0 70 1 1 8 0 P 1 1 1 1 0 0 0 0 61 0 0 0 O 1 0 1 0 0 1 12 0 0 1 13 1 1 01 O 1 0 18 1 1 L 0 1 P 151 1 O 1 10000 о 0

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 14VE

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