Suppose a byte-addressable memory with 4 frames of size 8 bytes each and a paged virtual memory using a three-entry TLB.Suppose a process P has 8 pages of virtual memory space. Assume the following TLB and page table for process P:TLBPage FramellFramet Valid1.121.Page TableAssume process P generates a memory request with virtual address 0X3A. What is its corresponding physical address? Youmay represent the address in binary or hexadecimal notation (if hexadecimal notation, prefix with Ox). If the request causes apage fault, enter page fault.

Answered: Image /qna-images/answer/f4a0fa73-3cf2-490e-a762-3d63b3201643.jpg

Suppose a byte-addressable memory with 4 frames of size 8 bytes each and a paged virtual memory using a three-entry TLB. Suppose a process P has 8 pages of virtual memory space. Assume the following TLB and page table for process P: TUB Page Framell 7. Frame Valid 1. 4. Page Table

Suppose a byte-addressable memory with 4 frames of size 8 bytes each and a paged virtual memory using a three-entry TLB. Suppose a process P has 8 pages of virtual memory space. Assume the following TLB and page table for process P: TUB Page Framell 7. Frame Valid 1. 4. Page Table

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Assume the following scenario for multi-level paging used by a process that has following: a. Logical Address = 64 bits b. Page size = 1 M Byte c. Page table entry size = 4 Byte d. System is byte addressable. calculate the following. 1. Logical Address Space? 2. Maximum number of page table entries in a single page? 3. How many levels of page table entries will be used? 4. Compute the size of page tables at each level? 5. Compute the number of entries in a single page? 6. Compute the number of pages
For an old computing system with 2K bytes physical memory, and the virtual address has 13bits. Suppose that the size of page/frame is 256 bytes. For a process A, it has its codes and data inpage 0, 1, 2, 10, 11, 28, 29, where pages 0, 1, 10, 29 are in frame 1, 3, 4 and 6, respectively.Moreover, frame 0 contains kernel OS code/data and all other frames are free.a. Show the page table and the content of each PTE for process A;b. Use a figure to illustrate the address translation for virtual address 1110000100000 and explainwhat happens during the translation (interaction among page table, physical memory, disk, andoperating system);c. Suppose that there is a TLB with 4 entries and the current content has the mapping informationfor pages 0, 1. Draw a new figure to illustrate the translation of address 101000011000 andexplain what happens during the translation process.
Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?
Consider a virtual memory system that can address a total of 32 bytes. You have unlimited hard disk space, but are limited to only 16MB of semiconductor (physical) memory. Assume that virtual and physical pages are each 4 KB in size. What is the total size of the page table in bytes? (Assume that, in addition to the physical page number, each page table entry also contains some status information in the form of a valid bit (V) and a dirty bit (D)).
In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Virtual Address (bits) Physical DRAMInstalled Page Size PTE Size (byte) 43 16 GiB 4 KiB 4 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss?
Suppose you have a byte-addressable virtual address memory system with 16 virtual pages of 64 bytes each and 4-page frames. Assuming the following page table, answer the questions below: Page # Frame # Valid bit 0 2 1 1 3 1 2 - 0 3 0 0 4 1 1 5 - 0 6 - 0 7 - 0 A. What physical address corresponds to the virtual address 0x42? Answer should be in hexadecimal number. (if the address causes a page fault, answer as "page fault" with the proper explanation) B. What physical address corresponds to the virtual address 0x72? Answer should be in hexadecimal number. (if the address causes a page fault, answer as "page fault" with the proper explanation) C. What physical address corresponds to the virtual address 0x84? Answer should be in hexadecimal number. (if the address causes a page fault, answer as "page fault" with the proper explanation)
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
) Consider the following sequence of virtual memory references (in decimal) generatedby a single program in a pure paging system:100, 110, 1400, 1700, 703, 3090, 1850, 2405, 2460, 4304, 4580, 3640a. Derive the corresponding reference string of pages (i.e. the pages the virtual addressesare located on), assuming a page size of 1024 bytes. (Assume that page numberingstarts at 0)b. For the page sequence derived above, determine the number of page faults for each ofthe following page replacement strategies, assuming that two (2) page frames areavailable to the program.i. LRUii. FIFOiii. OPT (Optimal)
Assume a 32-bit address system that uses a paged virtual memory, with a page size of 2 KB, and a PTE (Page Table Entry) size of 1 B. Answer the following questions, assuming a virtual address 0x00030f40 a. What is the virtual page number (VPN) and the offset in binary for the given virtual address? b. How many virtual pages are there in the system?
You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, Show the address format for virtual address 0x12 (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. (Hint: Convert the address to its binary equivalent and divide it into the appropriate fields.) Explain how these fields are used to translate to the corresponding physical address.
1. Consider a computer system with a 30-bit logical address and 4-KB page size. The systemsupports up to 512 MB of physical memory. How many entries are there in each of the following?Assume that each page table entry is 4 Bytes.c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? 2. Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address.Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes.a. How many frames are in the systems? How many pages in the virtual address space for aprocess?b. If a single-level page table is deployed, calculate the size of the page table for each process.c. Design a multilevel page table structure for this system to ensure that each page table can fitinto one frame. How many levels do you need? Draw a figure to show your page systems
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. Could you hand draw the page table, if possible a) Suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) b) What is the size of the two-level page table