You are given the following data about a virtual memory system: (a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1 nsec). (b) A page table entry can be found in 100 clock cycles or 100 nsec. (c) The average page replacement time is 9 msec. If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-translation time?

You are given the following data about a virtual memory system: (a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1 nsec). (b) A page table entry can be found in 100 clock cycles or 100 nsec. (c) The average page replacement time is 9 msec. If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-translation time?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter5: Data Storage Technology

Section: Chapter Questions

Problem 2PE

See similar textbooks

Similar questions

You are given the following data about a virtual memory system:(a)The TLB can hold 1024 entries and can be accessed in 1 clock cycle (1 nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 6 msec.If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-translation time?
You are asked to perform capacity planning for a two-level memory system. The first level, M1 is a cache with three capacity choices of 64Kbytes, 128Kbytes, and 256Kbytes. The second level, M2, is a main memory with a 4Mbyte capacity. Let c1 and c2 be the costs per byte and t1 and t2 be the access times for M1 and M2, respectively. Assume c1 = 20 * c2 and t2 = 10 * t1. The cache hit ratios for the 3 capacities are assumed to be 0.7, 0.9 and 0.95, respectively. What is the average memory access time, AMAT, if t1 = 20ns in the three cache designs? (Note that t1 is the time from M1 to CPU and t2 is that from M2 to CPU. This means that t2 includes t1).
a) In the SRAM region, what is the corresponding bit-band alias address for the bit [4] of the memory address of 0 * 2000008 b) In the Peripheral region, if the value in the alias address 0 * 4200 0088 to 0 * 4200 008B was set to 0x00000001, what is the bit # and the address in the peripheral region that wants to set to 1?
If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?
Q3 Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Next-Fit? Assume the last allocated hole is 20K.
Draw the mapping cache memory for this system and view the details of the connection between cache memory and main memory with this parameter ? Cache is divide into two memories (one for data and another for instruction) Cache size 16 bytes (8 for data 8 for instruction) Block line size 16bytes Main memory size is 16Mbytes and each byte addressing to 24 bit address Cache design 2-way set associative
Suppose we have a system with 8-byte words and a cache with 32-byte blocks connected directly to memory. The cache has a hit time of 10 ns. The bus to memory is 8 bytes wide, requesting a word from memory takes 100 ns (total, aka round trip time), and memory bus transactions are serialized (not pipelined). The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only 20%. Show your work. (a) What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block (25% chance of each). This means that 25% of misses are for word 1 in a block, 25% for word 2, 25% for word 3, and 25% for word 4. (b) What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is 5%, 15%, 30%, and 50%, respectively? (c) What is the AAT speedup over baseline with…
The PowerPC uses a hardware managed TLB with an inverted page table. Discuss its advantages and disadvantages. i.e., What are the implications of the inverted page table on the size of each page table entry? What about a page table walk (how many memory references are potentially required on a TLB miss)? Are per-process page tables necessary or can they be eliminated?
A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?
Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?
Given a system with separate instruction and data caches, suppose the frequency of data operations is 0.31. Given a HitTime of 1ns for each cache and a miss penalty of 50ns for each cache, calculate the average memory access time (in nsec). Assume that the miss rate for the data cache is 0.08 and the miss rate for the instruction cache is 0.04.Round your answer to two decimal places
A certain processor uses separate instruction and data caches with hit ratios 97% and 94% respectively. The access time from the processor to either cache is 1 clock cycle, and the block transfer time between the caches and main memory is 67 clock cycles. Among blocks replaced in the data cache, 21% is the percentage of dirty blocks (Dirty means that the cache copy is different from the memory copy). Assuming a write-back policy, what is the AMAT for the instructions in this system? Round to 2 decimal places.