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- Assume a computer has on-chip and off-chip caches, main memory and virtual memory. Assume the following hit rates and access times: on-chip cache 95%, 1 ns, off-chip cache 99%, 10 ns, main memory: X%, 50 ns, virtual memory: 100%, 2.5 ms. Assume that an acceptance effective access time is 1.6 ns. What should X be (the percentage of page faults) to ensure that EAT is no worse than 1.6 ns?Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?Consider a three-level memory system, where the access time for the cache is T1 nanoseconds, main memory access time is T2 microseconds, and disk access time is T3 milliseconds. Main memory hit ratio is estimated to be 40%. a) What are the minimum and the maximum possible access times? Show your work. b) If the cache hit ratio H is 60%. What is the relation between T1, T2, and T3 to achieve an average access time less than 10 * T1. Show your work.
- A computer has four page frames. The time of loading, time of last access, and the Referenced (R) and Modified (M) bits for each page frame are shown in Table 1 (the times are in clock ticks from the process start at time 0). A page fault to virtual page 4 has occurred at time 265. Table 1: Virtual Page Information Including the initial placement of virtual page in memory (as in Table 1) just before the page fault, consider the following virtual page reference string: 1, 2, 3, 0, 4, 0, 4, 3, 1, 2, 0, 5, 2, 4, 1 Referring to Table 1, which page should be replaced for each of the following memory management policies? Explain why the page is replaced. FIFO LRU Optimal (Refer to the reference string) How many page faults would occur if Optimal policy is used? Show clearly when each page fault would occur.A system with 6 computer process, P1, P2, P3, P4, P5, P6. their current time stamp 7, 5, 8, 9, 5, 6. All have a common variable X. P2 , P3 and P5 wanted to access X. what wait time will require P2, P3 and P5 use X, assuming each will access X for 1s, and each message passing will require 1s and process time also 1s. use Ricart-Agarwal algorithm suppose P7 failed at 7s, What will be the total time to get the new leader in this ringConsider the following set of processes, with the length of the CPU burst and I/O burst given in milliseconds: Process CPU, I/O, CPU Arrival time P1 2, 3, 1 0 P2 2, 1, 4 4 P3 1, 1, 4 10 P4 6, 6, 6 13 For example: In FCFS a process p1 arrived at 0 ms gets CPU for 2 ms, then releases CPU to the next process for 3ms where it performs I/O burst and return back to the queue with a new arrival time as (2+3 = 5ms) 5 ms. In case of a tie, go with process number. Perform the following for FCFS and non-preemptive SJF scheduling algorithm: Calculate the average waiting time, average turnaround time. With respect to each metric justify which scheduling algorithm is good for the given process mix.
- Consider a CPU that services processes arriving (following Poisson distribution) at an average rate of 20 processes/second. Assume that the average service time (following exponential distribution) for the processes is 40 milliseconds. Answer the following questions: (a) What is the expected utilization of the CPU? (b) What is the average number of processes you expect to see in the system (waiting in the Ready Queue and get (c) What is the average turnaround time of these processes you expect to see? (d) How many processes, on average, you expect to see waiting in the Ready Queue?Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?The overhead required to read an entry in a page table (including the time to access TIB) is 60 nanoseconds. To reduce this overhead, the computer has a TIB that can hold 16 entries and be accessed in 10 nanoseconds.a) Let B = TLB lookup time, T - memory cycle time, and p = hit ratio. Finda formula that expresses the effective access time.b) What hit ratio is needed to reduce the effective access time to 70 nanoseconds?
- 3 A computer has 1000K of main memory. The jobs arrive and finish in the sequenceJob 1 requiring 200K arrivesJob 2 requiring 350K arrivesJob 3 requiring 300K arrivesJob 1 finishesJob 4 requiring 120K arrivesJob 5 requiring 150K arrivesJob 6 requiring 80K arrivesAmong the best fit and first fit, which performs better for this sequence?The various operations in a computer are stored either in the cache or memory. Franko phones, a computer assembly plant in Ghana has come out with a three level cache computer. If their computer has main memory access time 1200nsand the first, second and third caches have 500ns, 400ns and 200ns access times respectively. If h1, h2 and h3 are respectively 0.7, 0.6 and 0.5a) Generate an equation for computing the average access time of the new computer.Using your equation determine the average access time. Assuming cache 2 goes down, but this does not affect the operation of the computer, refine your equation in “a” above and compute the new average access time. explain how you arrived at your answer.a single process, with execution time of BT time units, is detected by the system that uses Round Robin algorithm with time quantum of QT time units. Every time the time quantum elapses; a contect switch is always performed with CS time units. Assume that the process come at time equal to zero(0) If BT is 25, QT is 10 and CS is 2, what is the Cpu utilization of the system? If BT is 20, QT is 6 and CS is 1 what is the CPU utilization of the system? What is the CPU utilization if BT is equal QT and QT is equal to CS? What is the system's throughput if BT is less than QT? What is the system's turnaround time (TAT) if BT is less than QT?