Write an ARM assembly code procedure that finds min integer in a given array of positive integers. Notes: 1) Each element of the input array is two bytes long. 2) A student needs to make suitable assumption about the base address and the size of the input array. 3) A student may utilize any general purpose register in the ARM CPU. 4) The procedure returns the min in X12 register.
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- To write an assembly program of ARM subroutine, which returns to register R0 the number of odd elements in the second part of the array (from the middle to the end) of an array of even number of words with start address and number of elements respectively registers R0 and R1.For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)Here is the question about mips.Q1). Suppose $s0 stores the base address of word array A and $t0 is associated with m, convert the following instruction into MIPS. A[240] = A[240+m]Q2). Suppose $t0 stores the base address of word array A and $s0 is associated with m, convert the following instruction into MIPS. m= 0 while (m <= 10): A[m] = A[m+4]*6 m = m + 6
- Will upvote! Find the memory address of the next instruction executed by the microprocessor, when operated in the real mode, for the following CS:IP and 80286 register combinations: a. DS=2F2E & DX=9D64 b. CS=9F7A & IP=AB27 c. ES=DE21 & DI=D75F d. SS=FF5C & BP=92B8 e. DS=DC67 & CX=2FE8dont use AI to do itQ1). Suppose $s0 stores the base address of word array A and $t0 is associated with m, convert the following instruction into MIPS. A[240] = A[240+m]Q2). Suppose $t0 stores the base address of word array A and $s0 is associated with m, convert the following instruction into MIPS. m= 0 while (m <= 10): A[m] = A[m+4]*6 m = m + 5write a subroutine (in assembly) for ARMcortex-A9 that 1. accepts a memory address A passed in register r0 2. Sum the words incrementing from address A, until the accumulating sum would be considered a negative number ( A is first address read). 3. Return the final value in r 0 . Should preserve state of system using the stack pointer (sp). If you are unable to write Assembly code to complete this problem, please use comments and/or pseudocode as much as possible to describe what should be done.
- Please answer the following; a. What registers are implicitly changed by an x86 call instruction in what way? b. Write an x86 assembly code to implement the following function based on known array offsets. An optimal solution is 3 lines of assembly including the return. //add two specific elements int f(int a[a][2]){ return a[0] [1] + a[2] [1]; }In the Intel 8086 microprocessor, suppose the register AX contains the data 35AB H. What will be the contents of AX after executing the following programs? Assume that the initial content on the Carry Flag (CF) is one for all the calculations. You MUST clearly show ALL your steps in obtaining your final result for getting full and/or partial credit. Please present your final result in Hexadecimal format. (a) MOV CL,04H SHR AX,CL RET (b) MOV CL,04H RCR AX,CL RET1. T/F - if (B)=006000 (PC)=003600 (X)=000090, for the machine instruction 0x032026, the target address is 003000.2. T/F – PC register stores the return address for subroutine jump.3. T/F – S register contains a variety of information such as condition code.4. T/F – INPUT WORD 1034 – This means Operating system should reserve 1034 bytes in memory5. T/F - In a two pass assembler, adding literals to literal table and address resolution of local symbol are done using first pass and second pass respectively.
- Suppose we have the instruction Load 0000. Given memory and register R1 contain thevalues below:R130Memory Address Content0000 40...0010 30...0020 78...0030 55...0040 77...0050 84 Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator using the following addressing modes: a. Immediateb. Directc. Indirectd. Indexed6. Suppose that the interrupt processing method of is to store the breakpoint in the address of 00000Q unit, and fetch the instruction from the 77777Q unit (that is the first instruction of the interrupt service routine) and execute it. Write the micro-operations sequence that completes this function.Please help with the following in regards to Nand2Tetris, and hack code, so hack assembly and hack vm. There can be more that one answer to a question if so please explain why. 1a. The A-instruction in the Hack computer performs a. direct addressing. b. immediate addressing. c. indirect addressing. d. bitwise addressing. 1b. Each memory address in the Hack computer references a. a single byte. b. a single word. c. multiple words. d. the D-register 1c. Given the following assembly code: (FOO) @FOO 0;JMP The purpose of the code is to : a. test of the value is = = 0 NO-OP b. jump to address 0 in RAM c. return a 0 to the calling code d. create an endless loop e. end the assembly language program 1d. Given a function called foo() that calls another external function bar() which in turn calls a second function called additup(). Indicate the VM line of code indicating the location in the program that control should be return to: a.@Foo.$bar. b. @Foo$bar$additup.ret.1 c.…