Given the following assembly language program and its equivalent machine language code where some references are missing. The assembler generates a relocatable code. All references use direct addressing. Write the values of the location counter (LC) and the contents of the symbol table, and also fill in the missing references in the machine code. (Assume that 3 bytes are allocated for each instruction and WORD pseudo-operation allocates 3 bytes and stores the given number at that byte.) Q.8. START LC Machine code INST1 00 00 Symbol Table ЗА L1: INST2 D1 D5 ?? ?? JZR L1 7B ?? ?? HLT 4C 00 00 D1: WORD 00 00 05 END

Consider memory storage of a 64-bit word stored at memory word 32 ina byte-addressable memory(a) What is the byte address of memory word 32?(b) What are the byte addresses that memory word 32 spans?(c) Draw the number 0xF1234567890ABCDE stored at word 32 in both big-endianand little-endian machines. Clearly label the byte address corresponding to eachdata byte value.

Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 6 bits, memory addresses are 64 bits, data size is 32 bits and register addresses are 5 bits. a. For each instruction set architecture shown in Figure A.1, how many addresses or names (including both memory and register), appear in each instruction for the code to compute C = A+ B, and what is the total code size? passor TOS Memory (A) Accumulator (C) Registry (D) Re loed oore Figure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the oper and is an input or the result of the orithmetic-logical unit ALU operation, or both an input and result Lighter shoes indicate inputs, and the dark shode indicates the result in a top of stack (TOS) register points to the top input operand, which is combined with the operand below. The first operand is removed from the stack, the result takes the place of the…

Please solve and show all work. For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 8-byte words: f = (g+i+2) + (h − 8);          B[8] = A[i-9] + A[j+8] + 7;

(a) In MIPS machine language, the R format instructions need an additional field (the “funct” field) to specify the instruction type (“add”, “sub”, etc.). Why can’t this be done using just the 6-bit “op” field, which all MIPS instructions have, instead? (b) Give a sequence of MIPS assembly language instructions that adds the contents of $s0 and $s1, storing the result into $s0, if the contents of $s1 are greater than 6. Otherwise, the contents of $s0 should be incremented by 28. In either case, afterwards the contents of $s0 should be copied into $s2. (c) Suppose that the starting address of an array of words is stored in $s0. Give a MIPS assembly language instruction that loads the contents of the second word in the array into $s1. (d) Suppose that A and B are defined using “A: .word 0”, and “B: .space 100”. Give a sequence of MIPS assembly language instructions that calls a procedure “P” with its two arguments being the contents of A and the address of B, using the standard procedure…

The stack segment, data segment, and code segment are all separate entities. Next, ascertain which combination of registers is used to address data items inside each segment.

E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code

18 What is speculation as it relates to parallelization? It is the set of instructions that issues together in one clock cycle and the packet may be determined statically by the compiler or dynamically by the processor. It is a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. It is the number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline. O It is an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.