lab5 report

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University of Illinois, Urbana Champaign *

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Dec 6, 2023

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ECE 385 Fall 2023 Experiment #5 Simple Computer SLC-3.2 in SystemVerilog Hank Zhou & Yuxuan Ma TY/Friday 13:45

Tianhao Yu

1. Introduction a. Summarize the basic functionality of the SLC-3 processor In this lab, we were tasked with designing an SLC-3 Processor using the SystemVerilog programming language. The SLC3 system consists of both onboard memory and a central processing unit. This processor has the capability to perform fundamental arithmetic and logic operations such as addition, bitwise AND, and XOR. Additionally, it can load data from memory and store data into memory. Moreover, it offers branching functionality, allowing for the execution of looping operations, which are crucial for sorting algorithms and similar tasks. This microprocessor is a simplified version of the LC-3 ISA and shares key characteristics such as a 16-bit Program Counter (PC), 16-bit instructions, and a set of registers. The SLC-3 Processor was capable of executing various operations based on a specific set of opcodes, which were a subset of the LC-3 ISA opcodes. Its architecture closely resembled that of the LC-3, including the datapath and state machine diagram, but omitted the logic and states associated with TRAP instructions. In Lab 5.1, our primary focus was on implementing the FETCH phase, while Lab 5.2 involved the implementation of both the DECODE and EXECUTE phases. By successfully creating and integrating these three phases, we were able to complete the SLC-3 microprocessor. 2. Written Description and Diagrams of SLC-3 a. Summary of Operation We have successfully implemented 11 distinct operations that our SLC-3 processor can execute based on the opcodes present in the Instruction Register (IR). These operations include ADD, ADD with immediate value (ADDi), AND, AND with immediate value (ANDi), NOT, BRANCH (BR), Jump (JMP), Jump to Subroutine (JSR), Load Register (LDR), Store Register (STR), and a PAUSE operation. Our processor operates with a 16-bit architecture and carries out three primary phases: fetching an instruction from memory, decoding the instruction to determine its type, executing the instruction, and then repeating the process by fetching the next instruction. b. Describe in words how the SLC-3 performs its functions. You should describe the Fetch-Decode-Execute cycle as well as the various instructions the processor can perform. The SLC-3 processor operates through a cycle consisting of three main states: Fetch, Decode, and Execute. The cycle begins with the Fetch state, where the Program Counter (PC) is loaded into the Memory Address Register (MAR), and the PC is incremented. Subsequently, the CPU retrieves data from Static Random-Access Memory (SRAM) at the address stored in MAR and

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loads it into the Memory Data Register (MDR), which is then written into the Instruction Register (IR). Moving to the Decode state, bits 9-11 of the IR are compared with a 3-bit value stored in a register, which may be used in branch operations. The next state is determined by the four-bit opcodes (bits 12-15) of the IR. This information is input into the Instruction Sequencing and Decode Unit (ISDU) to generate the appropriate signal for the next state. In the Execute phase, different instructions are carried out based on specific instruction codes stored in memory and provided by the user. For operations like ADD, ADDi, AND, ANDi, and NOT, the SLC-3 performs computations involving the contents of Source Registers 1 (SR1) and Source Register 2 (SR2), or an offset, and the result is stored in a Destination Register (DR). For BR (branch) instructions, the branch condition (BEN) is determined during the Decode state. If BEN is equal to 1, the offset is added to the PC, and the processor executes the instruction at the memory location indicated by the updated PC. In the case of LDR (Load Register) and STR (Store Register) instructions, data is read from or written to memory in the SRAM. For JMP and JSR (Jump to Subroutine) instructions, the PC either jumps directly to a specified memory location, or in the case of JSR, the PC is stored in Register R7, and then incremented. The Pause instruction involves waiting for user input. It triggers an LED to light up and waits for the user to input a value using a switch. The processor remains paused until the user presses the "continue" button, at which point it resumes from state 18. After each execution, the state returns to state 18, completing the cycle. c. Block Diagram of slc3.sv

Figure1: Block Diagram of SLC d. This diagram should represent the placement of all your modules in the slc3.sv. Please only include the slc3.sv diagram and not the RTL view of every module (individual expansions can go into the individual module descriptions). e. Written Description of all .sv modules i. A guide on how to do this was shown in the Lab 2.2 report outline. Module: ALU Inputs: [15:0] SR1OUT, [15:0] SR2OUT, [15:0] IR40, [2:0]ALUK, SEL Outputs: [15:0] ALUOUT Description: The system takes two inputs, SR1OUT and SR2OUT, and performs one of four possible operations on these inputs based on the value of the selection signal (SEL). The available operations are: AND, ADD, NOT, and a simple pass-through operation for SR1OUT.

Purpose: The Arithmetic Logic Unit (ALU) serves as the computational component that carries out the execution process for two register values, producing a result that is stored in a register. It plays a fundamental role in the processor's operation. Module: tristate Inputs: Clk, tristate_output_enable, [15:0] Data write Outputs: [15:0] Data read inout wire: [15:0] Data Description: This component functions as a buffer with the capability to either retrieve data from SRAM and send it to MEM2IO or store data in SRAM. When the tristate output enable is not active, it will produce a high-impedance value. Purpose: This module can establish connections between both the MEM2IO and SRAM ports, facilitating bidirectional data transfer for both read and write operations through an inout wire data bus. Module: slc3 Inputs: [15:0] S, Clk, Reset, Run, Continue Outputs: [11:0] LED, [6:0] HEX0, [6:0] HEX1, [6:0] HEX2, [6:0] HEX3, [6:0] HEX4, [6:0] HEX5, [6:0] HEX6, [6:0] HEX7, CE, UB, LB, OE, WE, [19:0] ADDR Description: This module encompasses all the components of the SLC-3 and essentially represents the SLC-3 itself. It comprises the datapath module, which includes various smaller components, the MEM2IO module, and the state machine. The hex signal is employed to showcase the written data. Purpose: This module serves as the SLC-3 processor, capable of executing instructions fetched from memory. Module: MEM2IO Inputs: Clk, Reset, [19:0] ADDR, CE, UB, LB, OE, WE, [15:0] Switches, [15:0] Data from CPU, [15:0] Data from SRAM Outputs: [15:0] Data to CPU, [15:0] Data to SRAM, [3:0] HEX0, [3:0] HEX1, [3:0] HEX2, [3:0] HEX3

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Description: This module is responsible for handling all input and output devices, specifically the switches and 7-segment displays. Purpose: Its primary function is to oversee the management of input values from switches and output values to hex drivers. Module: test_memory Outputs: [15:0] mem array[0:size-1] Description: The memory contents stored in the test memory. Purpose: It is exclusively utilized for simulation purposes, serving as a substitute for SDRAM. Module: lab6 toplevel Inputs: [15:0] S, Clk, Reset, Run, Continue Outputs: [11:0] LED, CE, UB, LB, OE, WE, [19:0] ADDR, [6:0] HEX0, [6:0] HEX1, [6:0] HEX2, [6:0] HEX3, [6:0] HEX4, [6:0] HEX5, [6:0] HEX6, [6:0] HEX7 Description: It is the top level file of the project. Purpose: This file acts as a simulator for an SLC-3 module and establishes a connection to the test memory, which serves as a substitute for SRAM during the simulation. Module: HexDriver Inputs: [3:0] In0 Outputs: [3:0] Out0 Description: It manages the inputs to be displayed on the HEX display. Purpose: It displays wanted data on the HEX display of the FPGA board. Module: MUX4_1 Inputs: [15:0] A, [15:0] B, [15:0] C, [15:0] D, [3:0]sel Outputs: [15:0] Out Description: A multiplexer (MUX) that determines which one of four gate values can be directed into the bus.

Purpose: This MUX is employed to select the appropriate gate value, ensuring that only one gate is open at any given time. Module: MUX4_1_16bit Inputs: [15:0] A, [15:0] B, [15:0] C, [15:0] D, [1:0] S Outputs: [15:0] Out Description: A MUX that accepts four distinct sign-extended bits from the Instruction Register (IR). Purpose: This MUX is utilized to select the precise number of IR bits that need to be combined with addr1mux. Module: MUX2_1 Inputs: [15:0] A, [15:0] B, [15:0] C, [15:0] D, [1:0] S Outputs: [15:0] Out Description: A MUX that receives four distinct sign-extended bit inputs from the IR. Purpose: This MUX's purpose is to select the appropriate number of IR bits that will be added to addr1mux. Module: MUX3_1 Inputs: [15:0] A, [15:0] B, [15:0]C, [1:0] S, Outputs: [15:0] Out Description: The MUX employed for the Program Counter (PC) allows us to select the input data for the PC. Purpose: This MUX is utilized to determine the specific operation that updates the PC, which is subsequently loaded into the PC register. Module: MUX2_1_3bit Inputs: [2:0] A, [2:0] B, [1:0] sel, Outputs: [2:0] Out Description: The MUX used for SR1MUX allows us to designate the data that enters the SR1OUT register.

Purpose: This MUX is employed to pick different bits from the IR instruction depending on the situation. When dealing with the STR (Store Register) instruction, the MUX selects IR[11:9], while for other instructions, it selects IR[8:6]. Module: NZP Inputs: Clk, LD CC, LD BEN, BUS VAL, [2:0]IR911 Outputs: BEN Description: This logic is responsible for loading the NZP (Negative, Zero, Positive) values from the bus and storing them in the NZP register when the "LD CC" (Load Condition Code) signal is active. It then performs a bitwise AND operation with the instruction bits in the IR to compute the correct NZP values. Purpose: In the case of a BR (Branch) instruction, it's essential to examine the condition bits to decide whether a jump to a particular location is necessary. After setting the Condition Code (CC) following each operation, such as ADD, AND, and others, the logic performs a comparison between the condition bits specified in the BR instruction and the previous result to determine if the result is negative, positive, or zero. Module: Register Inputs: Clk, Reset, Load, [15:0] Din Outputs: [15:0] Dout Description: It is a 16 bit register. Purpose: Utilized in MDR, MAR, and any registers requiring storage of 16-bit values. Module: Register12 Inputs: Clk, Reset, Load, [11:0] Din Outputs: [11:0] Dout Description: It is a 12 bit register. Purpose: Utilized in registers designed for the storage of 12-bit values. Module: Register3 Inputs: Clk, Reset, Load, [2:0] Din

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Outputs: [2:0] Dout Description: It is a 3 bit register. Purpose: Utilized in registers designed for the storage of 3-bit values. Module: Register_file Inputs: input LD REG, Clk, Reset, [2:0] DRMUXOUT,[2:0] SR1MUXOUT, [2:0]SR2, [15:0] BUS VAL, Outputs: [15:0] SR2OUT,SR1OUT Description: This is a register file consisting of registers ranging from R0 to R7. Each of these registers can be accessed for both reading and writing by providing an input address. Purpose: This register file operates similarly to on-chip memory, allowing data to be stored in R0 to R7 and retrieved for use in SR1OUT and SR2OUT. Module: flip_flop Inputs: Clk, Reset, Load, Din Outputs: Dout Description: It is a D flip-flop. Purpose: Employed within the NZP module, this component loads the logical result of NZP into a BEN flip-flop, which serves as the storage for the Branch Enable bit value. Module: SEXT Inputs: [N-1:0]IR Outputs: [16:0]OUT Description: This module serves the purpose of sign-extending specific bits of the IR. Purpose: It is employed when the input of ADDR1MUX needs to be combined with an offset, as defined within the IR instruction. Module: datapath Inputs: LD_MAR, LD_MDR, LD_IR, LD_BEN, LD_CC, LD_REG, LD_PC, LD_LED, GatePC, GateMDR, GateALU, GateMARMUX, DRMUX, SR1MUX, SR2MUX, ADDR1MUX, MIO EN, [1:0] PCMUX, [1:0] ADDR2MUX, [1:0] ALUK, [15:0] MDR In, Clk, Reset

Outputs: BEN, [11:0] LED, [15:0] MAR, [15:0] MDR, [15:0] PC, [15:0] IR Description: This module integrates all the components within the SLC-3 and operates by receiving the appropriate input signals from the control unit. It then effectively transfers the correct data through MUXes or loads the appropriate data as needed. Purpose: With the datapath module, we have successfully interconnected all the components, including the control unit, within the SLC-3. The module outputs data to various destinations, such as LED, MAR, MDR, PC, IR, MUXes, and registers, ensuring that the correct data is received at the correct time. Additionally, it provides an interface with MEM2IO for simulation purposes. f. Description of the operation of the ISDU (Instruction Sequence Decoder Unit) i. Named ISDU.sv, this is the control unit for the SLC-3. Describe in words how the ISDU controls the various components of the SLC-3 based on the current instruction. ii. If you prefer to, you can lump this section into the module description section under ISDU.sv. Module: ISDU Inputs: Clk, Reset, Run, Continue, IR 5, IR 11, BEN, [3:0] Opcode Outputs: LD MAR, LD MDR, LD IR, LD BEN, LD CC, LD REG, LD PC, LD LED, GatePC, GateMDR, GateALU, GateMARMUX, DRMUX, SR1MUX, SR2MUX, ADDR1MUX, Mem CE, Mem UB, Mem LB, Mem OE, Mem WE, [1:0] PCMUX, [1:0] ADDR2MUX, [1:0] ALUK Description: This is the state machine that governs the entire operation of the SLC-3, including the Fetch, Decode, and Execute phases. It begins in a "halted" state and transitions to state 18 when the user presses the "RUN" button. From there, it commences the Fetch operation and automatically generates four fetch states before progressing to the Decode state (S_32). Based on the specific instruction stored in the IR, the Instruction Sequencing and Decode Unit (ISDU) proceeds to execute various states according to different opcodes. Input IR 5 is used in ADD and AND instructions to determine whether the CPU should add an offset or the value in a register, a decision controlled by the ISDU's output signal to the MUX. IR 11 is used in the JSP operation. Additionally, when ISDU enters state S_00 (the BR state), determined by input BEN, if BEN signal is 1, it advances to state S_22; otherwise, it returns to state S_18. In the case of the Pause state, if the opcode is 1101, ISDU enters a pause state after the Decode phase and awaits user input from the switch. The execution only continues when the user presses the "continue" button. In each state, if no input is required, the state generates the appropriate signals for the SLC-3, including the selection bits for MUX and Load signals. The state transitions to the next clock

cycle after processing. If the user presses the "Reset" button, the system returns to the "halted" state and clears all signals, regardless of the current state. Purpose: The control unit plays a pivotal role in overseeing the entire operation of the SLC-3. It ensures that the correct output is generated for each state, guided by the input it receives. Collaborating with the Instruction Sequencing and Decode Unit (ISDU), the SLC-3 can execute various operations, manage data storage and retrieval from memory, and execute instructions stored in the memory. g. State Diagram of ISDU i. This should represent all states present in the ISDU and their transitions. The diagram from Patt & Patel Appendix C can be used as a starting point but would need to be modified to be representative of the ECE385 implementation of the LC-3. For example, how did you modify the FSM to account for the lack of an ‘R’ signal in the RAM. You will lose points if you just copy the diagram.

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Figure2: State Diagram of ISDU 3. Simulations of SLC-3 Instructions a. Simulate the completion of all 7 test programs, I/O Test 1, I/O Test 2, Self-Modifying Code, XOR, Multiplier, Auto Count and Sort.

b. Annotations for the above simulations should include at a minimum: start of the test program, any user input (for example, entering the numbers in the multiplier test), and reading the expected result. c. Note that for simulation traces which are long, you may truncate out the intermediate portions of the program. For example, you will likely need to do this so that your Sort test simulation is legible. Figure3: simulation of IO Test 1

Figure4: Simulation of IO Test2 Figure5: Simulation of Self-Modifying Test Figure6: Simulation of Auto-Counting Test Figure7: Simulation of XOR Test Figure8: Simulation of Multiplication Test

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Figure9: Simulation of Sort Test Before/After Sorting 4. Post-Lab Questions a. Fill out the Design Resources and Statistics table from Post-Lab question one LUT 670 DSP 0 BRAM 0.5 Flip-Flop 270 Latches 0 Frequency 90 Static Power 0.078 Dynamic Power 0.019 Total Power 0.097 b. Answer all the post-lab questions. As usual, they may be in their own section or dispersed into the appropriate sections in the rest of the report. 1. What is MEM2IO used for, i.e. what is its main function? MEM2IO acts as the intermediary connecting the SRAM module and the SLC3 processor, effectively bridging the gap between the memory on the FPGA board and the FPGA chip. It facilitates data reading from the switch and the subsequent display of output data on the HEX display.

2. What is the difference between BR and JMP instructions? The JMP instruction allows the PC to change without any conditions; it simply jumps to the location specified by the address contained in the BaseR register. In contrast, the BR instruction requires a specific condition to be met before the PC changes. It takes a branch if any of the condition codes match the condition stored in the status register; otherwise, it continues with its regular execution. The branch location is determined by adding the sign-extended PCoffset9 to the current PC. In addition, the JMP instruction accepts address data from a register, while the BR instruction receives the branch address from the IR. 3. What is the purpose of the R signal in Patt and Patel? How do we compensate for the lack of the signal in our design? What implications does this have for synchronization? The R signal is employed to indicate the readiness of the memory. It is an indicator that, when activated, signifies the completion of memory access and the readiness of data for processing. In our design, as we didn't have this signal, we introduced an additional state at state 33, creating two states, 33_1 and 33_2. The first state, 33_1, serves to introduce a clock cycle to ensure that the memory is ready, while the second state, 33_2, is responsible for providing signals just as the original state 33 did. The transition between states is no longer dependent on the R signal. Our design ensures that there's one clock cycle before transitioning to state 33_2. This approach extends the wait time, eliminating the need for an additional synchronizer. Because the states no longer rely on an R signal to be raised and all states that involve waiting operate for the same number of cycles, our processor is considered asynchronous. 5. Conclusion a. Discuss functionality of your design. If parts of your design did not work, discuss what could be done to fix it. Our design is operating flawlessly. In the first week, we successfully executed the FETCH operation, with MAR, MDR, and IR functioning smoothly. In the second week, we expanded our operations to include tasks such as AND, XOR, multiplication, and sort. b. Was there anything ambiguous, incorrect, or unnecessarily difficult in the lab manual or given materials which can be improved for next semester? You can also specify what we did right, so it doesn’t get changed. The instructions provided in this Lab are highly explicit and clear. While the Lab itself is challenging and complex, the guidance proved to be immensely valuable throughout the design

process. The concept of using MUX as an alternative to the tri-state buffer design was particularly insightful, as it inspired us to explore alternative methods to achieve the same functionality. However, there were certain inconveniences during the debugging phase. The waveforms to be examined were extensive and intricate, requiring a substantial amount of time to verify the correctness of each operation. As a result, we believe that having explicit answers included in the waveforms would greatly assist in the debugging process.

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