HW7csc 137-25AryaAswini
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California State University, Sacramento *
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137
Subject
Computer Science
Date
Dec 6, 2023
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docx
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5
Uploaded by PresidentPolarBearMaster17
Arya Aswini
HW#7
CSc 137
(25 points)
P1. In order to minimize the duration of a read cycle, the _oe can be asserted at any time
within a maximum time after the _ce is asserted, as illustrated in the timing diagram.
(5 pts)
A.
True
B.
False
P2. A memory write cycle is similar to a read cycle, except that data must be placed on the
data bus at the same time that _ce is asserted or within a maximum delay after _we is
asserted to minimize the time the data bus is used. Figure 7.17 illustrates an SRAM memory
write cycle.
(5 pts)
I.
A memory cycle is initiated by which component in the computer motherboard?
The CPU (Central Processing Unit) is the part of the computer motherboard that starts
the memory cycle.
II.
A memory cycle, typically, how many CPU clock cycles to complete?
It takes about 2 clock cycles, the first for placing the data over the data bus and the
second for sending the data over the data bus.
7.10
Consider a 32-bit data bus SDRAM.
Given that the clock frequency of the bus is
200MHz, what is the peak memory bandwidth in megabyte per second (MBs)?
(5 pts)
7.11
Consider a 64-bit data bus SDRAM.
Given that the clock frequency of the bus is
200MHz, what is the peak memory bandwidth in megabyte per second (MBs)?
(5 pts)
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Related Questions
A memory write cycle is similar to a read cycle, except that data must be placed on the
data bus at the same time that _ce is asserted or within a maximum delay after _we is
asserted to minimize the time the data bus is used. Figure 7.17 illustrates an SRAM
memory write cycle. (20pts)
A. A memory cycle is initiated by which component in the computer motherboard?
B. Generally, how many CPU clock cycles does it take to complete a memory cycle?
Address Bus
Valid Address
_ce
_we
Maximum time
_oe 1
Data Bus
Valid Data
Write Access Time
One write cycle
FIGURE 7.17 An SRAM write cycle from a memory point of view.
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] The following sequence of 16-bit control words are presented to the datapath. For each, identify the microoperation that is executed as an RTL expression. Assume that Memory Write (to the RAM) is NOT asserted unless it is explicitly indicated. (a) x0001 (b) x4251 (c) xFFFE, MW asserted
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3. The contents of memory location B0007H are FFH and those at BO00AH are
O0H. What is the data word stored starting at address B0008H? Is the word
aligned or misaligned? And how many cycles are used to transfer this word if (a)
BS16' is negated (b) BS16' is asserted?
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1) given the size of the word accessible
main memory is 1KB and the size of the
word is 16-byte, the total number of the
registers is 64, what is the minimum number
of wires of the address bus?
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A computer employs RAM chips of 512 x 4 and ROM chips of 256 x 8. The computer
system needs 1KB of RAM, and 512 x 8 ROM and an interface unit with 256
registers each. A memory-mapped I/O configuration is used. The two higher -order
bits of the address bus are assigned 00 for RAM, O1 for ROM, and 10 for interface.
a) How many lines must be decoded for chip select? Specify the size of the decoder
b) Draw a memory-address map for the system and Give the address range in
hexadecimal for RAM, ROM
c) Develop a chip layout for the above said specifications.
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12. Draw the Timing diagram for INR M.
> Fetching the Opcode 34 from the memory 4105H.
Let the memory address (M) is 4250H.
Let the content of that memory is 12H.
> Increment the memory content from 12μ to 13μ-
Address
4105
Mnemonics
INR M
Opcode
34H
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The address bus consists parallel signal lines
while data bus consists separate lines.
True
O False
Hardwired control units are generally faster
than micro - programmed designs. *
True
False
The main property of a bus is that it is a
shared transmission medium. *
True
O False
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Subject: Computer Organization and ArchitectureTopics Covered: IA-32 Architecture
SEE ATTACHED PHOTO FOR THE PROBLEM
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Section [error correction and detection] 1 of3
Upload answer sheets
Design a decoder which selects the register files of a processor where it has registers from R0 to R15. Assume a 8-bit data word 11011001
is stored in memory. Using an appropriate technique determine the error check bits that would be stored in memory along with the data
word. During memory read operation, a LSB (Least Significant Bit) gets modified. Explain how does the technique correct the error?
uolcuour suhmission
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6- In 8086Mp bus cycles, the signal (ALE) becomes '1' during
clock cycle.
7- The type of the buffer used for buffering data lines is
while the type of
the buffer used for buffering address lines is
8- During transferring a data of 8-bits from 8086Mp to memory address (1F871H),
give the logic value of the following signals:
M/IO=
RD=
=
WR=
BHE=
9- The benefit of multiplexing operation is
1. CC
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Difference between address bus & data bus is:
Select one:
a. Address bus is bidirectional while data bus Is unidirectional.
b. Data wires are only for data signals.
C. None of the options given here.
d. Both carry bits in either directions.
e. Address bus is only for addressing signals.
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Q5
(a)
Based on situations below, explain the control signal sequence:
(i) Transfer the address of PC to Memory Address Register (MAR).
(ii) Transfer the words in memory to Memory Buffer Register (MBR).
(b)
Write micro operation for the following instructions:
(i)
ADD AC, х
(ii)
ADD X,(A)
(iii)
MOV CX,
(CHAR)
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Q:
State the differences between write bus cycle in memory in and read in
Input/Output.
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Computer Architectecture [CR-CE325]
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Combine the flowcharts that appear in Figures 4.11 and 4.12 so that the interrupt checking appears at a suitable place.
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Q: If data is to be sent from an input device to a memory buffer starting at address A000H and ending at AFFFH, provide the mode byte for DMA channel 2.
Check that p is not totally disconnected from the bus throughout the DMA cycle.
Furthermore, the channel is to be reinitialized at the conclusion of each DMA cycle such that the same buffer is filled when the next DMA operation is initiated?
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1. Status register in PIC's contains arithmetic status of
2. The
is one of SFR in PIC's, but it is not a physical register.
3. PCH register in PIC116F877a is indirectly writable through
4. In PIC16F877a the address of reset vector is
register.
and the adress of interrupt vector
is
5. A PIC16F877a has
ports, each one can be identify as input or output by instruction
and you can control on port level (1 or 0) by instruction
6. The Control Word Register in 8253 PIT can only be
into; no
For 8086 MP, the instruction that compares two specified bytes or words is
7.
8. For 8086 MP, the instruction that converts byte in AL to word in AX is
9. For a segment register is (E1B2H), and offset value is (1225H), the physical address is
equal to
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(d) A process wishes to transfer to main memory n bytes of data from an I/O device
which can internally buffer up to b (b
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PCSrc
ID/EX
EX/MEM
Control
IF/ID
Add
Branch
MEM/WB
Add
Shift
left 2
RegWrite
Instruction
Memory
Read
Address
Read Addr 1
Register Read
Read Addr Data 1
File
Write Addr
Data
Memory
MemtoReg
ALUSrc
Address
Read
Data
ALU
Read
Data 2
Write Data
Write Data
ALU
cntrl
MemRead
Sign
Extend
16
32
ALUOP
RegDst
Figure 3: For EACH of the following registers, indicate how many bits are in the reg-
ister, and what control signals are are in the register. he control signals in the diagram
are: regWrite, regDest, aluOP, ALUsrc, Branch, MemRead, MemWrite, MemToReg.
Register
Number of bits
Control Signals
PC
32
None
IF/ID
64*
None
ID/EX
EX/MEM
МЕM/WB
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Please solve it fast
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None
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Good explanation please
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Computer Science
A computer uses a memory of 64K words with 16 bits in each word.It has the following registers: PC, AR, TR, AC, DR and IRA memory-reference instruction consists of two words: an 16-bit operation-code(one word) and an address field (in the next word).a-List the sequence of microoperations for fetching a memory reference instructionand then placing the operand in DR. Start from timing signal To.b-Design the logic control gates arrangement to perform the fetch instructions.
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1) Jump and Jump and Link instructions have a six-bit op-code and a 26-bit jump address field. How is the full 32-bit Jump Address calculated?
The jump address field is sign-extended six bits to the left.
The leftmost four bits of the PC are concatenated with the jump address field, and two bits of zero are concatenated to the end of that.
The leftmost six bits of the PC are concatenated with the jump address field.
The jump address is ANDed with Register 0 to produce the jump address.
--------------------------------------------------------------------------------
2) How is a branch target address calculated?
Sign-extend bits 15:0 of the instruction, append two bits of zeros, and add the result to the PC.
Zero extend bits 15:0 of the instruction, append two bits of ones, and subtract the result from the PC.
Add the immediate operand to register zero, and sign extend the result.
Concatenate the leftmost 16 bits of the PC with the rightmost 16 bits of the instruction.…
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Digital system design
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Related Questions
- A memory write cycle is similar to a read cycle, except that data must be placed on the data bus at the same time that _ce is asserted or within a maximum delay after _we is asserted to minimize the time the data bus is used. Figure 7.17 illustrates an SRAM memory write cycle. (20pts) A. A memory cycle is initiated by which component in the computer motherboard? B. Generally, how many CPU clock cycles does it take to complete a memory cycle? Address Bus Valid Address _ce _we Maximum time _oe 1 Data Bus Valid Data Write Access Time One write cycle FIGURE 7.17 An SRAM write cycle from a memory point of view.arrow_forward] The following sequence of 16-bit control words are presented to the datapath. For each, identify the microoperation that is executed as an RTL expression. Assume that Memory Write (to the RAM) is NOT asserted unless it is explicitly indicated. (a) x0001 (b) x4251 (c) xFFFE, MW assertedarrow_forward3. The contents of memory location B0007H are FFH and those at BO00AH are O0H. What is the data word stored starting at address B0008H? Is the word aligned or misaligned? And how many cycles are used to transfer this word if (a) BS16' is negated (b) BS16' is asserted?arrow_forward
- 1) given the size of the word accessible main memory is 1KB and the size of the word is 16-byte, the total number of the registers is 64, what is the minimum number of wires of the address bus?arrow_forwardA computer employs RAM chips of 512 x 4 and ROM chips of 256 x 8. The computer system needs 1KB of RAM, and 512 x 8 ROM and an interface unit with 256 registers each. A memory-mapped I/O configuration is used. The two higher -order bits of the address bus are assigned 00 for RAM, O1 for ROM, and 10 for interface. a) How many lines must be decoded for chip select? Specify the size of the decoder b) Draw a memory-address map for the system and Give the address range in hexadecimal for RAM, ROM c) Develop a chip layout for the above said specifications.arrow_forward12. Draw the Timing diagram for INR M. > Fetching the Opcode 34 from the memory 4105H. Let the memory address (M) is 4250H. Let the content of that memory is 12H. > Increment the memory content from 12μ to 13μ- Address 4105 Mnemonics INR M Opcode 34Harrow_forward
- The address bus consists parallel signal lines while data bus consists separate lines. True O False Hardwired control units are generally faster than micro - programmed designs. * True False The main property of a bus is that it is a shared transmission medium. * True O Falsearrow_forwardSubject: Computer Organization and ArchitectureTopics Covered: IA-32 Architecture SEE ATTACHED PHOTO FOR THE PROBLEMarrow_forwardSection [error correction and detection] 1 of3 Upload answer sheets Design a decoder which selects the register files of a processor where it has registers from R0 to R15. Assume a 8-bit data word 11011001 is stored in memory. Using an appropriate technique determine the error check bits that would be stored in memory along with the data word. During memory read operation, a LSB (Least Significant Bit) gets modified. Explain how does the technique correct the error? uolcuour suhmissionarrow_forward
- 6- In 8086Mp bus cycles, the signal (ALE) becomes '1' during clock cycle. 7- The type of the buffer used for buffering data lines is while the type of the buffer used for buffering address lines is 8- During transferring a data of 8-bits from 8086Mp to memory address (1F871H), give the logic value of the following signals: M/IO= RD= = WR= BHE= 9- The benefit of multiplexing operation is 1. CCarrow_forwardDifference between address bus & data bus is: Select one: a. Address bus is bidirectional while data bus Is unidirectional. b. Data wires are only for data signals. C. None of the options given here. d. Both carry bits in either directions. e. Address bus is only for addressing signals.arrow_forwardQ5 (a) Based on situations below, explain the control signal sequence: (i) Transfer the address of PC to Memory Address Register (MAR). (ii) Transfer the words in memory to Memory Buffer Register (MBR). (b) Write micro operation for the following instructions: (i) ADD AC, х (ii) ADD X,(A) (iii) MOV CX, (CHAR)arrow_forward
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Recommended textbooks for you
- Systems ArchitectureComputer ScienceISBN:9781305080195Author:Stephen D. BurdPublisher:Cengage Learning
Systems Architecture
Computer Science
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Cengage Learning