cis501 spring 2019 final blank

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Page 1 of 7 CIS 501 – Computer Architecture Final Exam Prof. Devietti May 8, 2019 This exam is an individual-work exam. Write your answers on these pages. Additional pages may be attached (with staple) if necessary. Please ensure that your answers are concise and legible. Read and follow the directions of each question carefully. Please attempt to answer all the questions (don’t allow yourself to get stuck on a single question). You have 120 minutes to complete the exam. Please write your name/WPE-1 ID here and on the top of all pages. Name/WPE-1 ID:
Page 2 of 7 CIS 501 – Computer Architecture Final Exam Prof. Devietti May 8, 2019 1. [8 Points] Short Answer Answers should be at most 1 sentence. (a) What is Moore’s Law? [1 point] Moore’s Law states that the number of transistors per chip (or devices per integrated circuit) will double every 1-2 years. (b) LC4 is a 32-bit ISA true: ° false: ° [1 point] false, it’s 16-bit (c) Given a 5-stage pipeline (like in Lab 4) where each stage takes between 100-300 picoseconds, what is the clock period for this design? [1 point] 300 picoseconds picoseconds: (d) What special insns can be used to prevent insn reordering in a multicore? [1 point] memory fences, memory barriers (e) Which cache coherence protocol helps reduce the number of upgrade misses? [2 points] MESI (f) A TLB is used to accelerate what? [1 point] virtual memory, virtual=>physical address translation (g) Verilog® is the best programming language ever true: ° false: ° [1 point] false; credit given for any answer
Page 3 of 7 CIS 501 – Computer Architecture Final Exam Prof. Devietti May 8, 2019 2. [16 points] Grab Bag (a) Prof. Ross Esser wants to add a new subtract-immediate instruction to the LC-4 ISA. The instruction’s assembly syntax would be SUB Rd Rs IMM6 , and its semantics would be Rd = Rs - sext(IMM6) . Propose a way to encode this new instruction such that it does not conflict with any existing instructions, in the format used for the Encoding column for the LC4 ISA table. [2 points] 0011 ddd sss iiiiii (b) Given the Lab 5 superscalar pipeline, fill in a pipeline diagram for the instructions below, showing when each instruction reaches each stage and whether it is in the a pipeline or the b pipeline (see example in cycle 1). Use a * to indicate a stall (you don’t have to distinguish different stall types, e.g., superscalar versus branch misprediction). insn 1 2 3 4 5 6 7 8 9 10 11 STR r0 -> r1 #4 F a Da Xa Ma Wa LDR r0 <- r1 #5 F b Db Da Xa Ma Wa ADD r4 <- r2 r3 Fa Db Xb Mb Wb NOT r5 <- r0 Fb Fa Da * Xa Ma Wa [10 points] 1pt for STR, 3pts each for other insns (c) Dr. Carrie Luk, a head computer architect, asks you for the infinite-hardware CLA equation that computes a carry-out in terms of generate and propagate bits. Give a formula to compute the carry-out C 3 in terms of the initial carry-in C 0 and the various G j and P k terms. [4 points] ࠵? " = ࠵? % ∨ (࠵? % ∧ ࠵? * ) ∨ (࠵? % ∧ ࠵? * ∧ ࠵? , ) ∨ (࠵? % ∧ ࠵? * ∧ ࠵? , ∧ ࠵? , )
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