Revere Engineering In Linux

Develop a python program to generateclockpulsesfor the binary counterand the decoder.You should create a file including the following sequences: describe how you were able to make it and how come this code was successful. Thanks a million!

operatıng systemsThe figure on the right shows the operation of the read system call in general (count-read(fd,buffer,nbytes)).What does itmean if the operating system sends a value of 200 to the library procedure at arrow 9?

An address space in the memory map starts at address Ox40000000 and ends at address O×40000FFE. What is the size of the space if the data size is 2 bytes? 16k bytes 4k bytes 2k bytes 8k bytes

What causes diskthrashing in the first place? What actions may be taken to lessen its effects?

The following four requests could come in to an operating system as it is running on a computer system: The clock in the computer has just “ticked,” and we need to update a seconds counter. The program running on processor 2 is trying to perform an illegal operation code. Someone pulled the plug on the power supply, and the system will run out of power in 50 msec. The disk has just read the character that passed under the read/write head, and it wants to store it in memory before the next one arrives. In what order should the operating system handle these requests?

According to the memory view given below, if RO = 0x20008000, then LDRSB r1, r1 = ?(data overlay big endian)? Memory address Data Øx20008002 ØXA1 Øx20008001 ØXB2 Øx20008000 ØxC3 ØX20007FFE ØXD4 ØX20007FFE OXE5 (Ctrl) A-R1 = 0XC3 B-R1 = 0x000000C3 C-R1 = OXC3000000 D-R1 = 0xffffffC3 E-R1 = OxC3ffffff

Suppose a Unix Inode has 10 direct disk block pointers, one single indirect block pointer, one double indirect block pointer, and one triple indirect block pointer. For convenience, each index table has 256 = 28 entries and each block has 1K = 210 bytes. What is the maximum size of a Unix file in Kbytes?

The control signal Ep or iEnableoutput allows the program counter to decrement its value.  True  False The control signal Ep or iEnableoutput sends the content of the program counter to the W bus.  True  False   A tri-state buffer is needed for all data going to the W bus.  True  False   In using 'assign' statement in Verilog, the left hand side must always be a register.  True  False   In declaring a register in Verilog, the following format must be followed: reg [LSB:MSB] identifier;  True  False

answer for question 1

Interrupts are very important in Operating System, since they handle operation between devices and microprocessors. The scope of this homework is about interrupt in Linux, which is run on Intel X-86 platform. Based on references that has been distributed, you have to explain question belowfor me is about system clock Question: What is the IRQ assignment for the above device? How the process of interrupt between the device and the processor? What is the priority of the above IRQ? Explain about the interrupt vector of the above IRQ

If an address for a computer describes a memory having 4 x 230 bytes, how many gigabit of the computer are uniquely addressable? Hint: A Gigabyte is 230 bytes. A MegaByte is 2 20 bytes. 32Gbits 16GBbits SGBbits 4MBits

Suppose the OS on your computer uses the Buddy system for memory management. Initially the system has a 1 megabyte (1024K) block of memory available. Show the result of each request/release via successive figures similar to the one illustrated in the lecture slides. A: Request 25 K B: Request 500 K C: Request 70 K D:Request 100 K E: Request 40 K Release A F: Request 20 K Release B After memory is allocated to process F, how much internal fragmentation exist in the system.

A kernel object that is 5 KB in size will be stored in a(n) Q-KB slab. What is the value of Q?

Assume there is a PCI buffer that is used for data transfers between primary memory and a webcam. The memory transfers 15 frames where each frame is 1M byte in size and the buffer size is 1K byte. 1-How many data transfers will be required? 2-A transfer operation requires 2 interrupts. Start and stop. How many interrupts will occur for the data transfer? 3-What are the two commands that will be issued by the supervisor for each interrupt?

Memory Address Memory Content Øx20000013 Øx79 Øx20000012 Øxcd Øx20000011 Øxa3 Øx20000010 Øxfd ØX2000000F Өx12 According to the memory view given below, LDMIB r0 if RO = 0x20000004! after executing the {R7, r3, r9} Command, which of the following are the R9 and ro register contents in order (data placement big endian)? Øx2000000E Øxod ØX2000000D Øxe0 Øx2000000c Øxeb ØX2000000B Øx2c ØX2000000A Оx1а Øx20000009 Øxdc Øx20000008 Өx11 Øx20000007 Øx34 Øx20000006 Øxce Øx20000005 Øxfd Øx20000004 Øxe4 Øx20000003 Оха2 Øx20000002 Øx3f Øx20000001 Øx06 Øx20000000 Øxf5 Lütfen birini seçin: O A. R9= 0X79CDA3FD r0 = Ox2000000C O B. R9= 0X11DC1A2C r0 =0x20000010 O C. R9= 0XEBE0OD12 r0 =0x2000000C O D. R9= 0X120DEOEB r0 =0x2000000C O E. R9= 0XFDA3CD79 r0 =0x20000010

What data does the PSR contain? O The current privilege level, the values of N, Z, and P, and the current priority level. the PC and all the General Purpose Registers O The PC, the values of N, Z, and P, and the stack pointer O The PC, MDR and IR the PC and the MCR (Machine Control Register)

% A Q1: the smallest addressable entity is called? * Your answer Q2: if address bus is 9 bits, then the size of memory is. . bytes * Your answer Q3: if memory size is 1KB, and word length is 32 bits. How many words are stored in the memory? * Your answer Σ

I was curious in how Linux handled virtual memory.

Every rotation of a motor causes a switch to be pushed. The switch, like most mechanical switches, 'clatters' or bounces when the contacts come together, causing an interval when a single press causes multiple closures. This bouncing can continue for just under 3 milliseconds. The switch is linked into the memory map of a 68000 processor at bit 0 of location $FFFFF000. It is connected so that the bit will read a '1' when the switch is open, and a '0' when closed and not bouncing. The bouncing will cause alternating zeros and ones. For ease of any analysis you do, assume that every instruction takes 1 usec., regardless of addressing mode. If the switch were connected to a falling-edge-sensitive interrupt request line what problem could result during the bouncing? And what is one way the problem might be solved?

Every rotation of a motor causes a switch to be pushed. The switch, like most mechanical switches, 'clatters' or bounces when the contacts come together, causing an interval when a single press causes multiple closures. This bouncing can continue for just under 3 milliseconds. The switch is linked into the memory map of a 68000 processor at bit 0 of location $FFFFF000. It is connected so that the bit will read a '1' when the switch is open, and a '0' when closed and not bouncing. The bouncing will cause alternating zeros and ones. For ease of any analysis you do, assume that every instruction takes 1 usec., regardless of addressing mode.

Which registers does the CPU automatically save on the stack when responding to an exception request?   List the changes in memory and CPU core registers after the CPU responds to an exception request but before it executes the first instruction of the exception handler

Malware uses various techniques to covertly execute code on systems. One such technique is DLL injection. DLL injection involves causing code to execute within the address space of some other process. This is accomplished by forcing the targeted program to load a DLL. Why are malware hiding techniques like DLL injection successful? Shouldn't the operating system have built-in controls to prevent DLL injection? Shouldn't anti-malware software be able to detect and prevent DLL injection 100 percent of the time?