Lab12_Y86

. Assume SP=0XE99D, R16=0XE2, R17=0x25, R01=0XFC, R15=0X1F and the following memory information. Address contents (hex) post Address contents (hex) post pre 22 pre 44 OXE996 OXE99C OXE997 46 OXE99D C5 OXE998 17 OXE99E Аб OXE999 21 OXE99F 77 ОхЕ99A F2 OXE9A0 78 OXE99B C3 OXE9A1 A5 Find the values of the registers SP, R01, R16 and R17 after the following operations. РОP R01 РО R16 РОP R17 РOP R20 PUSH R15 SP R16 R17 R01 R20 R15

Suppose r0 = ox300010A0, r2 = 0x00000011, and the memory layout is as follows Address: Data: 0x300010A7 0x72 0x300010A6 0XA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0XA5 0x300010A0 0x01   -What are the values of r0 and r1 after executing the following code? Illustrate your process in a memory map. LDR r1, [r0], #3 ADD r1, r1, r2 STR r1, [r0, r#4]

Suppose r0 = ox300010A0, r2 = 0x00000011, and the memory layout is as follows Address: Data: 0x300010A7 0x72 0x300010A6 0XA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0XA5 0x300010A0 0x01   -What is the Value of r0 and r1 after executing LDR r1, [r0, #2]   -What are the values of r0 and r1 after executing the following code? Illustrate your process in a memory map. LDR r1, [r0], #3 ADD r1, r1, r2 STR r1, [r0, r#4]

Given the following assembly code snippet, assume = $9000. Line #: memory address Assembly code 00: 00001000 LEA $6000, A1 01: 00001004 MOVE.W #%1000000000000001, (A1)+ 02: 00001008 MOVE.W #%1100000000000011, (A1)+ 03: 0000100C MOVE.W #%1110000000000111, (A1)+ 04: 00001010 MOVE.W #%1111000000001111, (A1)+ 05: 00001014 MOVE.W #%1111100000011111, (A1) 06: 00001018 LEA $6000, A1 07: 0000101C MOVE.B #0, DO 08: 00001020 LOOP1 MOVE.W (A1)+, D1 09: 00001022 AND.W #$00FF, D1 10: 00001026 LSR #1, D1 11: 00001028 MOVE.W D1, -(SP) 12: 0000102A ADDQ.B #1,DO 13: 0000102c CMP.B #5, DO 14: 00001030 BLT LOOP1 15: 00001032 LEA $6000, A1 16: 00001036 MOVE.B #0, DO 17: 0000103A LOOP2 MOVE.W (SP)+, (A1)+ 18: 0000103C ADDQ.B #1,DO 19: 0000103E CMP.B #5, DO 20: 00001042 BLT LOOP2 Answer the following questions, provide all values in hexadecimal. 1. What is the value of the PC while executing instructions #12 and #18? 2. What is the calculated displacement at instruction #14? Explain your answer. 3. What is…

SP=1239H, SS=9876H, the physical address is OAAAFH O AAAFOH O 1всобн о O H66666 The instruction JMP BX is a * direct jump True O False O

intel 8086 microprocessor

Below is a list of 64-bit memory address references given as word address. Ox03, Oxb4, Ox2b, Ox01, Oxb7, Ox58, Oxbe, Ox02, Oxb5, Ox2e, Oxb6, Ox5b 0000 4 0100 8 1000 1100 1 0001 5 0101 9 1001 d 1101 2 0010 6 0110 a 1010 e 1110 3 0011 7 0111 b 1011 f 1111 Given a direct-mapped cache with 16 word blocks, what is the hit ratio? O 0.5 O 1 O 0.75 O 0.25

x86-64 bit Assembly

What will be the value of ALUSrc for add instruction Inst[25–21] rs Read register 1 ALU operation Read data 1 Inst[20–16] n MemWrite Read register 2 Registers Read Write register MemtoReg Zero ALU ALU result Inst ALUSrc Read data Address data 2 Inst[15–11]| Write data Write data Data memory RegDst RegWrite 16 MemRead Sign extend Select one: а. О b. None С. 1 d. X

LCPU assignment Multiply the number by 1.25: A = X * 1.25X = 0x3C (direct). Then save the result to main memory using direct addressing. Example: Multiply the value by 0.75: X * 0.75 = 0.5 * X + 0.25 * X X = 100 (0x64)100 * 0.75 = 750x64 = 01100100 00110010 [Shift 1x to the right - add 0 to the left and cut off one bit from the right]00011001 [Shift 2x to the right - add 00 to the left and truncate 2 bits from the right]01001011 [Sum of previous two transactions] 01001011 = 0x4b = 75

Q6: A digital computer has a memory unit with 24 bits per word. The instruction set consists of 110 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. (a) How many bits are needed for the opcode? (b) How many bits are left for the address part of the instruction? (c) What is the maximum allowable size for memory? (d) Can we extend this instruction set by adding new 10 instructions and keeping the same length of opcode part? (e) Determine the type of this instruction set: stack-based ISA or accumulator- based ISA or general purpose registers-based ISA?

Computer science

Write code on C or C++.

What will be the value of ALUSrc for add instruction Read register 1 Read register 2 Registers Read Inst[25-21] | ALU operation Read data 1 | MemWrite MemtoReg Inst[20–16] t Zero ALU ALU result Inst ALUSrc Write register Read data Address data 2 Inst[15–11) Write data Data Write data memory RegDst RegWrite | MemRead 16 Sign 32 extend Select one: а. X b. 0 О с. 1 O d. None

For the 8086 microprocessor, show the physical addresses and the contents of memory after execution of the following directives, if DS=A800H.DATA1 DW 65DATA2 DD 0A4718HDATA3 DD 6E000CHDATA4 DB 2 6 , 3 1 , 0FFh, 0 1 1 1 1B

Below shows the following hexidecimal values:Address 1000: 13Address 1001: 03Address 1002: C5Address 1003: 00 Provide the format and assembly language instruction for the following hexadecimal values.

Consider a memory implemented for 8086 microprocessor Draw the memory block diagram. Determine the values for A0 , /BHE ,address lines(A1..A19) and data lines(D0.. D15) in order to access: A byte at odd address [01FF3H] A byte at even address [01FFCH] A word at even  address [01FFEH] A word at odd address [01ABFH]

Suppose that the CPU is tasked to read data "X" from RAM with an address "C7FFF" and write the same data to RAM with an address "C8FFF" to replace data "Y." Describe in your own words how data X overwrites Y in RAM.

DEBUG shows the address 807C:010F. The corresponding physical address is ______.

Q8/Assume that the microprocessor can directly address 64K with a R/W' and 8 data pins The memory map for 16K x 8 RAM system that design by using 4Kx8 RAM are * None of them EFFF-E000, DFFF-D000 ,BFFF-B000,7FFF-7000 E7FF-E700,D7FF-D700 ,B7FF-B700 ,A7FF-A700 EFFF-E000,DFFF-D000 ,BFFF-B000,AFFF-A000 E7FF-E700,D7FF-D700 ,B7FF-B700,77FF-7700

physcal addresses are 4s ng 4 Ame dat in a cetain compe, te addresses can be translaled without y TLB entries At most how many ditina vid the address translation peh has 12 vld The Translation Look aside Bulfer (TLB)i sine is kB and the word size iby The memory is word addresible. The pe virtual addresses are 64 bea long d th sine is miss?

For the UART architecture shown below for your reference, what should be the ready condition when CPU is writing to UART? UART Paral undefined Serial out Buffer Empty Tx Data Buffer Data Bus Buffer Full Rx Data Butter Serial in Serial-inParallel-out Shift Register TX Data Buffer empty RX Data Buffer empty TX Data Buffer not full RX Data Buffer full

ISA of a hypothetical CPU 1 Address Memory: Address Data - (8-bits) LOAD M 100 25 STORE M 101 90 ADD M 102 65 SUB M 103 36 MUL M 104 22 105 77 DIV M 106 89 Where: Note: all numbers are hexadecimal M-a memory address AC - accumulator Sample program: //line 1 /line 2 //line 3 //line 4 //line 5 //line 6 LOAD 100 ADD 101 STORE 106 LOAD 102 SUB 103 STORE 105 Answer the following questions based on the given information above. 1. What is the content of memory location 106 after executing line 3? 2. What is the content of memory location 105 after executing line 6? 3. Write a program segment that will multiply the content of memory location 105 with the content of AC and store the result at memory location 100. а. b. 4. For this CPU, what is the width of the program counter? (express answer in terms of bits, do not include the word "bits" in your answer)

Consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes (like LC-3): ADDRESS OxFFFF OXOCOE OXOCOD Ox0C0C OXOCOB OXOCOA 0x0C09 0x0000 CONTENTS 1111 1111 1111 1111 1111 1110 1101 1100 0001 1011 1100 0101 0110 0101 1000 0111 1100 0000 0100 0000 0011 0001 0101 0010 0000 1100 0000 1101 0000 0000 0000 0000 The table above shows the addresses in hex (base 16) and the contents at the corresponding address in binary (base 2). A.) What are the contents in hex of the memory location at following address in binary: 0000 1100 0000 1110? (Enter hex like the following example: Ox2A3F)

The MSP430X family (X stands for eXtended) can handle a larger amount of memory since it has a 20-bit wide address bus. This family of processors is built based on a von Neumann architecture and is byte-addressed as well. What is the maximum number of bytes that can be addressed? Enter a decimal value.

Computer architecture