CEG 2138 Lab1

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University of Ottawa *

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2138

Subject

Electrical Engineering

Date

Feb 20, 2024

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pdf

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7

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Lab 1 CEG 2138 - Computer Architecture I Fall 2022 School of Electrical Engineering and Computer Science University of Ottawa September 22nd, 2022 Index Figure 1.0 - Theoretical Truth Table…………………………………………………………………….3 Figure 1.1 - Experimental Circuit………………………………………………………………………..4 Figure 2.0 - Function of the Full Adder…………………………………………………………………4
Figure 3.0 - Circuit Part III.I in Quartus…………………………………………………………………5 Figure 3.1 - Functional Simulation………………………………………………………………………5 Figure 3.2 - Timing Simulation…………………………………………………………………………..6 Figure 3.3 - Circuit Part III.II in Quartus………………………………………………………………...7 Theoretical Part In this lab, we are designing a simple circuit which we assume to be a full adder. The importance of this type of circuit is the fact that it is a very important basis for being able to create more complex circuits in the future. The principle of a full adder of this sort is to be able 2
to “hold” a binary digit in its flip-flop and then “give it back” to the circuit to be able to add and increase the number (+1). This being said, an adder of this sort has many drawbacks, to name a few, the adder can only increase by a step of 1, and cannot subtract (hence the name “adder”). Regardless, this is a very important fundamental circuit which isn’t too complicated to grasp while still having interesting results. In this lab, we weren’t asked to solve a problem, we were rather asked to follow a series of instructions to experimentally verify our theoretical truth table (Fig. 1.0) of the experimental circuit (Fig. 1.1) and show that they correlate. This circuit consists of 3 inputs, 2 XOR gates, 2 AND gates, one OR gate and 2 outputs. We will use these gates in Quartus to prove our design. Figure 1.0 - Theoretical Truth Table 3
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