ht2383_matlab_HW9_report

What is a multipath channel? Why is a multipath channel frequency selective?

Decoder circuit as shown in the following Figure. if A is LSB and C is MSB, the output expression F= YO Y Y, Y, D. Y. Decoder O a. B' O b. C O'c.B O d. C

What Is branch datapath?

6) This QUESTION FROM Information theory course. just write for me the the correct answer.

We want to design a digital circuit that converts Gray code (ABC) to Binary code (xyz). Set up a 8-to- 1 line multiplexer so that the output gives y as a function of ABC. "A" is given to the most significant bit of the control inputs of the multiplexer. "C" is given to the least significant bit of the control inputs of the multiplexer.

Please solve it fast

what is Successive approximation ADC? please explain

What are the shortcomings of one dimensional parity error detection scheme? And discuss the advantages of Two-dimensional parity over single parity scheme?

To implement a Full Subtracter, Using TWO 8:1 Multiplexers (ONE for Sum output and ONE for Cout output). Assign (or Connect) X, Y,and Bin variables to the Select Inputs of Multiplexers and connect 1 or 0 to each Data Input.

• The input to the Encoder is (1), _lines and the output is (2) _lines. • The input to the Decoder is (3). input lines and (4)_ output lines. The multiplexer has (5), output and (6). _inputs.

VHDL

See the figure below for Manchester scheme on CH-1 of Scope. Write the corresponding input bit stream. DE

Proper detailed explanation in text else ready for downvote!!

Explain the disadvantages of digital telecommunication.

Implement a full-adder circuit with a decoder and two OR gates. C-- - the f.

Perform the following functions:a. What will be the parity of the data signal to send as even parity:10100111001b. (0101)BCD = (---?---)2 = (---?---)Excess-3 = (---?---)Grayc. How to represent following numbers in signed representation:1. (-78)102. (-19)10

I need the answer as soon as possible

What causes quantization noise?

What is meant by CRT ?

Suppose that the circuit shown in the below figure is to be modeled. What is the correct VHDL option for the synthesis of this circuit? global_resetb zb- global cik a

Implement 8-bit asynchronous ripple counter and showing truth table, timing diagram. Also show how it can be used as frequency divider?

Given that the base address is FoH. 1. Create a new asm project “Lab2_Q1.asm". Assume that port A of 8255A PPI is connected to 8085. Write assembly code to send the value of FFH to FoH. Enter a delay of 2 ms for each transmission.

Choose the correct answer low HDOP (Horizontal Dilution of Precision) number such as2 indicates a ........................... a.poor fix b.good fix c.poor signal quality d. good signal quality

There exists one or more discrete ime signal. What is it control system ? (a) discrete time or (b) continuous time

(i) Below (figure 1) is an example of a VHDL code for a multiplexer. --multiplexer.vhd --Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(el, d3, d2, d1, d0 : IN STD_LOGIC; a,b.c,d,e,f.g.h.ij.k,lm,n:OUT STD LOGIC); END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC_VECTOR (13 downto 0); BEGIN input ca el & d3 & d2 & d1 & d0; WITH input SELECT "00000010000001"WHEN "10000",--Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010",- "00000010000001"WHEN "10011",- "00000011001111"WHEN "10100" "00000011001111"WHEN "10101 "00000011001111"WHEN "10110" "00000011001111"WHEN "10111" "10011110000001"WHEN "11000" "10011110000001"WHEN "11001" "10011110000001"WHEN "11010, "10011110000001"WHEN "11011" "10011111001111"WHEN "11100" "100111110011i1"WHEN "11101",- "10011111001111"WHEN "11110",-- "10011111001111"WHEN "11111":-. "00000010000001" -00 --"00000011001111"-01…