Lab Report_EET130-1

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ECPI University, Virginia Beach *

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201707E

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Electrical Engineering

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Feb 20, 2024

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EET130 Digital Systems I Instructor: Todd Lemon Lab 1 Signals and Number Systems Student Name(s): Carly Hribar Honor Pledge: I pledge to support the Honor System of ECPI. I will refrain from any form of academic dishonesty or deception, such as cheating or plagiarism. I am aware that as a member of the academic community, it is my responsibility to turn in all suspected violators of the honor code. I understand that any failure on my part to support the Honor System will be turned over to a Judicial Review Board for determination. I will report to the Judicial Review Board hearing if summoned. Carly Hribar Date: 11/18/2023 Adding your name here constitutes your agreement to the Honor Pledge as stated.

Contents Abstract ....................................................................................................................................................... 3 Introduction ................................................................................................................................................. 3 Part 1: Methods and Procedures .................................................................................................................. 4 Part 1: Results and Figures ...................................................................................................................... 4 Part 2: Methods and Procedures .................................................................................................................. 4 Part 2: Results and Figures ...................................................................................................................... 4 Conclusion ................................................................................................................................................... 5 References ................................................................................................................................................... 6 2

Abstract In this lab I will verify truth tables for common Logic Gates by constructing circuits in Multisim. I ntroduction This lab will demonstrate the properties of basic logic gates. It will also illustrate some of applications of Universal gates to implement functioning of other logic gates. I will construct common logic gates using Multisim and record the data to check the validity of the truth tables. 3

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Part 1: Methods and Procedures- Circuit 1: Circuit 1  1 – OR gate  2 – 1 KOhm resistors  2 – SPDT switches  1 – Digital probe  2 - VCC (5V)  2 – GND For circuit one I constructed a NOT gate circuit using the parts list above. Then used Multisim to test the validity of the predicted truth table. In Multisim I will change inputs A and B using SPDT switches and observe output using digital probe connected to output. Part 1: Results and Figures Table 1 Circuit 1 Results Input A Input B Predicted Output Measured Output 0 0 0 0 1 1 1 0 1 4

1 1 1 Part 2: Methods and Procedures- Circuit 2:  1 – AND gate  2 – 1 KOhm resistors  2 – SPDT switches  1 – Digital probe  2 - VCC (5V)  2 – GND Using these materials I will construct the AND Gate circuit and test the validity of the projected truth table with a probe. If there are any differences between “predicted” and “measured” output, I will find the error, and correct the problem. Part 2: Results and Figures Table 2: Circuit 2 results Input A Input B Predicted Output Measured Output 0 0 0 0 0 1 0 0 1 0 0 0 5

1 1 1 1 Part 3- Method and Procedure- Circuit 3: Parts:  1 – 74LS32N (OR gate IC)  1 – 74LS04N (Hex Inverter IC)  1 – 1KOhm resistor  2 – SPDT switches  1 – Digital probe  1 - VCC (5V)  1 – GND -Using Multisim I constructed the NOR Gate circuit using the parts listed. I then checked the validity of the truth table using a probe. -Place 74LS32N and 74LS04N into circuit and make sure VCC (pin14) and GND (pin 7) pins of both ICs are connected to 5V and ground, respectively. -Refer to data sheet for both ICs for pin layout. Connect pins 1 and 2 for 74LS32N to SPDT switches (to change inputs to high or low). -Connect pin 3 of 74LS32N to pin 1 of the 74LS04N. Next, connect digital probe to pin 2 of 74LS04N. Part 3: Results and Figures: Input A Input B Measured Output 0 0 1 0 1 0 6

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1 0 0 1 1 1 Part 4: Methods and Procedure- Circuit 4:  1 – 74LS08N (AND gate IC)  1 – 74LS04N (Hex Inverter IC)  1 – 1KOhm resistor  2 – SPDT switches  1 – Digital probe  1 - VCC (5V)  1 - GND I will use the parts listed in Multisim to construct a NAND Gate circuit. Part 4: Results and Figures: Table 4: Circuit 4 Input A Input B Measured Output 0 0 1 0 1 0 1 0 0 1 1 0 7

---Compare measured output in tables 3 and 4 and indicate the relationship between the two gates shown below. The measurements from both the circuits are the same. When both inputs are low there is a high output reading. Part 5- Methods and Procedures: Circuit 5- Parts:  1 – 74LS08N (AND gate IC)  1 – 74LS04N (Hex Inverter IC)  1 – 1KOhm resistor  2 – SPDT switches  1 – Digital probe  1 - VCC (5V)  1 - GND Using the parts list above I will construct a circuit similar to circuit 4. The IC chips will be reversed. I will the record the measurements on the table below Part 5- Results and Figures: 8

Table 5 Circuit 5 Input A Input B Measured Output 0 0 0 0 1 1 1 0 1 1 1 1 Part 6- Methods and Procedure- Circuit 6- Parts: 1 – 74LS32N (OR gate IC)  1 – 74LS04N (Hex Inverter IC)  1 – 1KOhm resistor  2 – SPDT switches  1 – Digital probe  1 - VCC (5V)  1 – GND In this circuit I will be using the parts list above to construct a circuit, measure the outputs and write the results in the table below. I will then compare Circuit 5 and Circuit 6. Part 6: Results and Figures- 9

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Input A Input B Measured Output 0 0 1 0 1 1 1 0 1 1 1 0 1. Compare measured output in tables 5 and 6 and indicate the relationship between the two gates shown below. According to the measured data, these have opposite output results. Where in Circuit 5 where any input was high, there was a high output; In circuit 6, if any output was low there was a high output. Conclusion In conclusion, the measured data from the OR, AND, NOR, NAND, and NOT gates coincide with the projected data. This confirms that and OR gate has a high output when either A input or B input are high. It confirmed that in an AND gate, the output is high when only both A and B inputs are high. For a NOR gate the output is high when either of the inputs are low due to it being a combination of an OR gate and a NOT gate (inverter). (As Shown in the broken down universal gate) This lab also confirmed that a NAND gate is the combination of an AND gate and a NOT gate. 10