Lab 1 Report

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University of Illinois, Urbana Champaign *

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385

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Electrical Engineering

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Dec 6, 2023

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pdf

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ECE 385 Fall 2023 Experiment #1 Introductory Experiment Hank Zhou TW/Friday 15:00-15:15 Jerry Wang

Purpose of Circuit: The main objective of this experiment is to provide us with an initial understanding of the ECE 385 laboratory and the equipment used within it. The key focus of this introductory experiment is to familiarize us with three essential pieces of equipment: the student lab kit, the oscilloscope, and the function generator. The circuits help us observe and eliminate static hazards. Description of Circuit: In Part A, we are utilizing a single 7400 chip, which has four NAND gates. The circuit has 3 inputs A, B and C, and 1 output Z. We set inputs A and C to a high voltage level of 5 volts, while input B is linked to a function generator producing a 1MHz square wave that ranges from 0 to 5 volts. The Boolean function describing the circuit is Z = B’C + AB. The circuit functions as a 2-to-1 multiplexer, where a high input on B results in the output being A, and a low input on B leads to the output being C. The intentional purpose behind this design was to expose a peculiar phenomenon known as a static-1 hazard. This anomaly implies the potential generation of a 0 pulse when a static logical analysis suggests that the output should remain at logic 1. BC A 00 01 11 10 0 0 1 0 0 1 0 1 1 1 In Part B, we revise the Part A circuit to remove any static-1 hazards in the output. To avoid static-1 hazard in the circuit, we need to cover all adjacent min-terms in the K-map. As the result, the Boolean function becomes Z = B’C + AB + AC. A 7410 chip is added to the circuit since we need a 3-input NAND gate. BC A 00 01 11 10 0 0 1 0 0 1 0 1 1 1

Logic Diagrams: Component Layout: Part A Circuit:

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Part A Result: Part B Circuit: Part B Result:

Answers to Pre-Lab Questions: 1. Not all groups may observe static hazards, why? Delay is so short that static hazard fails to change the output on LEDs. 2. Why does the hazard appear when you do this? The change of input B has delays in NAND gates, causing static-1 hazard. Answers to Lab Questions: 1. Does it respond like the circuit of part A? No. Glitch is eliminated. 2. For the circuit of part A of the pre-lab, at which edge (rising/falling) of the input B are we more likely to observe a glitch at the output? Falling. The Boolean function is Z = B’C + AB . Assume both A and C are at 1. During the falling edge of B, input B fall from 1 to 0. Due to the propagation delay in the NAND gate, it takes some time for the gate to respond to the falling edge of B. During this brief transition period, there's a possibility of a glitch, where the output Z may momentarily go to 0 before stabilizing at the correct value. In contrast, during the rising edge of B, input B rise from 0 to 1. Due to the delay, the output Z may momentarily go to 1, but this transition aligns with the normal operation of the NAND gate since we expect that the output should stay at logic 1.

Answers to Lab Questions: 1. The output Z takes 60 ns to stabilize on both the falling edge and the rising edge of B since the longest path from B to Z will pass 3 NAND gates. The glitches occur in those shadow areas where the output is uncertain, which are caused by NAND gates have propagation delay from input to output. 2. The de-bouncer circuit is designed to address the issue of contact bounce. When the switch is flipped, its contacts may bounce back and forth multiple times before settling into a stable position. To counteract this, the circuit utilizes two pull-up resistors to create a logic 1 for the gates. The switch connects one of the inputs to ground. When a switch is employed to clock a counter circuit, it has the potential to trigger multiple advancements of the counter with each flip of the switch. When the switch is in the high position, the output remains high regardless of the other input's value. This, in combination with the logic 1 produced by the bottom pull-up resistor, forces the lower NAND gate's input to zero. This zero signal then propagates back into the other gate. If the switch transitions between contacts and lingers in an uncertain state for a period, the latch maintains its current status due to the continuous zero signal generated by the bottom gate.

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Answers to questions from the General Guide: GG23: If we have two or more LEDs to monitor several signals, why is it bad practice to share resistors? Sharing resistors can affect performance of each LED. The current flowing through a resistor is determined by the voltage across it and its resistance value. When multiple LEDs share a resistor, changes in the voltage across one LED or the current flowing through one LED can impact the others. This can result in unpredictable behavior and may interfere with the signals that are monitored. GG7: A larger noise immunity indicates that a logic gate is more resilient to external noise and voltage fluctuations in its input signal. This enhanced immunity makes the circuit less susceptible to false or erroneous switching, which is crucial in digital systems where accuracy and reliability are paramount. The last inverter in a series is observed when measuring noise immunity because it represents the final output of the cascaded gates. Noise introduced at earlier stages can accumulate as it passes through the gates in series. By observing the output of the last inverter, you assess the cumulative effect of noise throughout the entire chain, providing a more accurate measure of the system's noise immunity. The noise immunity for logic 1 at the input is 3 – 2.15 = 0.85V, and the noise immunity for logic 0 at the input is 0.8 – 0.7 = 0.1V. So the overall noise immunity of the gate is 0.1V. Conclusion: This experiment helped us understand how and when the glitch occurs, provided us with several ideas to solve the glitch, and helped us familiarize ourselves with the use of CAD tools such as Fritzing.