quiz11-scratchwork

pptx

School

North Carolina State University *

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463

Subject

Electrical Engineering

Date

Dec 6, 2023

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pptx

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Uploaded by ProfessorRabbitPerson939

Quiz 11 “scratch work” NC State University Department of Electrical and Computer Engineering ECE 463/563 (Rotenberg) NCSU Honor Pledge: "I have neither given nor received unauthorized aid on this quiz." Student’s electronic signature: _______________________ (sign by typing your name)

Key add <dest. reg.>, <source reg. 1>, <source reg. 2> // 1 cycle in EX mult <dest. reg.>, <source reg. 1>, <source reg. 2> // 5 cycles in EX

Problem Setup • Consider a scalar OOO pipeline with a 3-entry IQ and 32-entry ROB. The pipeline is comprised of 9 stages as considered in class: FE, DE, RN, RR, DI, IS, EX, WB, RT.

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Question 1a 1a. Fill in the schedule for the following 6-instruction sequence. (i1 is fetched in cycle 1. i6 is fetched in cycle 10 due to an L1 I$ miss.) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 i1: mul r3, r1, r2 FE i2: add r3, r3, r4 i3: add r6, r5, r3 i4: add r3, r1, r4 i5: add r2, r3, r7 i6: add r3, r2, r3 (i6 missed in L1 I$, hence delayed fetch of i6) FE

Question 1b 1b. In the table below, for each source operand, indicate where the value was obtained from (select either ARF, ROB, or Bypass/IQ, by placing an “x” in the corresponding column). source reg. 1 source reg. 2 ARF ROB Bypass/IQ ARF ROB Bypass/IQ i1: mul r3, r1, r2 i2: add r3, r3, r4 i3: add r6, r5, r3 i4: add r3, r1, r4 i5: add r2, r3, r7 i6: add r3, r2, r3

Questions 2, 3, and 4 2.,3.,4.: Based on your schedule in Question 1a and the initial ARF contents below, show the pipeline state in cycle 10, cycle 13, and cycle 16. – Use the same format as in the lecture notes (show contents of structures and instructions as they appear within pipeline stages). – The pipeline is initially empty. – The ROB Head (H) and Tail (T) pointers are initially both at ROB entry 3 (H == T == rob3). – Use any free IQ entry as needed. – When showing IQ contents, you only need to show contents of valid instructions. – When showing ROB contents, you only need to show contents of instructions between H and T. – NOTE: As in the class notes, if the head instr. is in RT, it is being retired this cycle and assume the head pointer H has been incremented past it (no longer in ROB). For example: ILP1.pptx , Slide 83, Cycle 14, our “convention” is to consider rob3/i1 to not be in the ROB anymore as it is being retired (new H == rob4). This is the convention you must use in the Moodle quiz, please, for auto-grading. value r0 #-7 r1 #10 r2 #20 r3 #30 r4 #40 r5 #50 r6 #60 r7 #70 Architectural Register File (ARF)

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Decode Fetch Register Read Dispatch Issue Execute Writeback D$ agen Simple ALU Complex ALU Mem v ROB tag r0 r1 r2 r3 r4 r5 r6 r7 value r0 r1 r2 r3 r4 r5 r6 r7 value dst rdy exc.mis. pc rob0 rob1 rob2 rob3 rob4 rob5 rob6 rob7 … rob31 Rename Map Table (RMT) Issue Queue (IQ) Architectural Register File (ARF) Reorder Buffer (ROB) v dst tag rs1 rdy rs1 tag/value rs2 rdy rs2 tag/value tag (wakeup) data Rename Retire HT 7 CYCLE 10