studoclab9-an-introduction-to-high-speed-addition

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Texas A&M University *

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248

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Electrical Engineering

Date

Dec 6, 2023

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pdf

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6

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Studocu is not sponsored or endorsed by any college or university Lab9 - an introduction to high speed addition Introduction to Digital Systems Design (Texas A&M University) Studocu is not sponsored or endorsed by any college or university Lab9 - an introduction to high speed addition Introduction to Digital Systems Design (Texas A&M University) Downloaded by jon (jonelmama123@gmail.com) lOMoARcPSD|33974001
ECEN 248 - Lab Report Lab Number: 9 Lab Title: An Introduction to High-Speed Addition Section Number: 518 Student’s Name: Monica Long Student’s UIN: 530000823 Date: 11/04/2021 TA: Hung-Ta Chien Downloaded by jon (jonelmama123@gmail.com) lOMoARcPSD|33974001
Objectives: In previous lab we saw that delay can have a significant impact of speed, so in this lab we will be focusing on high-speed addition. We will learn how to implement high-speed addition using carry-lookahead and Verilog. The purpose of this lab is to be able to do addition with less delay than a ripple-carry adder. Design: I began the lab by copying the carry lookahead 4-bit test bench to simulate my carry lookahead 4-bit adder. After making sure all tests passed, I moved on to adding 2ns gate delays to my 4-bit carry lookahead adder to see what the propagation delay is. Then I wrote my block carry lookahead unit and expanded my generate/propagate and my summation unit to include 16-bits, to prepare to use them for a 16-bit carry lookahead adder. I then wrote my source code for my carry lookahead 16-bit adder and simulated it with the carry lookahead 16-bit test bench, making sure all tests passed. Then I modified my 16-bit carry lookahead adder to have gate delays of 2ns and changing TEST_DELAY in my test bench to my propagation delay from the first part, running the simulation over and over with decrementing the TEST_DELAY until tests fail. Results: During this lab I had no waveforms to include in my results, so my results will include my source code. Figure 1 is my generate propagate unit source code, Figure 2 is my carry lookahead unit source code, Figure 3 is my summation unit source code, Figure 4 is my carry lookahead 4-bit source code, Figure 5 is my block carry lookahead unit source code, and Figures 6 and 7 are my carry lookahead 16-bit source code. Figure 1. generate propagate unit source code Downloaded by jon (jonelmama123@gmail.com) lOMoARcPSD|33974001
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