Lab1- EEE

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Arizona State University *

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120

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Electrical Engineering

Date

Apr 3, 2024

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pdf

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9

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version 0.2 Spring 2024 1 CSE/EEE 120 Lab 1 Answer Sheet Half Adder, Full Adder, 4-bit Incrementer and Adder Name:____Aditya__ Instructor/Time:__Millman/ 3-4:15_________________________ Date:________2/6/2024_________________________________________________________________ _______ Task 1-1: Build and Test the 1-Bit Half-Adder Include a picture of your circuit in Digital here: Please comment on the single biggest issue you were facing when designing the circuit. Include a picture of your waveform (timing diagram) here:
version 0.2 Spring 2024 2 Did the circuit behave as expected? If no, what was wrong? - Yes, the circuit behaved as expected. Please comment on the single biggest issue you were facing when simulating the circuit. Task 1-2: Build and Test a 4-Bit Increment Circuit Include a picture of your circuit in Digital here:
version 0.2 Spring 2024 3 Please comment on the single biggest issue you were facing when designing the circuit. Include a picture of your waveform (timing diagram) here: Did the circuit behave as expected? If no, what was wrong? Yes it behaved as expected. Please comment on the single biggest issue you were facing when simulating the circuit.
version 0.2 Spring 2024 4 Task 1-3: Build and Test a 1-bit Full Adder Include a picture of your circuit in Digital here: Please comment on the single biggest issue you were facing when designing the circuit. Include a picture of your waveform (timing diagram) here:
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