HW-2

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University of Alabama *

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451

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Electrical Engineering

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Apr 3, 2024

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1. Here, V initial = 0V, V on = 50V, Rise time = 1ns, Fall time = 1ns, Period = 0.000025 s (1/F SW ), T on time = 0.000012 s ( Dutycycle *{1/F SW }). Fig-1: Circuit diagram. 2. Fig-2: Voltage at V sw node.
3. Output voltage (Vout) reach to steady state at approximately 10ms. Fig-3: Output voltage This can be calculated from the inductor current. From fig-4 it can be seen that the inductor current is steady state with respect to switching voltage after approximately 10ms.
Fig- 4: Switching voltage and inductor current. 4. The value of the overshoot of the output voltage when the converter is first turned on is approximately 42.1 V. Fig-5: output voltage for 50ms. 5. Charge, Q= 1 2 х time х height = 1 2 х ( 1 2 х 0.025 х 10 -3 s) х ( 1 . 56 2 A) = 4.875 х 10 -6 C Now, Q = C V ripple V ripple = 𝑄𝑄 𝐶𝐶 = (4.875 х 10 -6 C)/ (100 х 10 -6 F) = 0.04875 V
From the simulation the ripple voltage is appoximately 0.05V. So , the theoretically calculated value is very close to the value that one we got from simulation. Fig-6: ripple voltage 6. This system/filter is under-damped. Dumping ratio = 1 2𝑅𝑅 𝐿𝐿 𝐶𝐶 = 1 2 × 8 200 𝑢𝑢 100 𝑢𝑢 = 0.0884 7. The output voltage amplified if we change the switching frequency to 1.1KHz because 1.1KHz is the resonance frequency of the system. Resonance frequency, f c = 1 2𝜋𝜋√𝐿𝐿𝐶𝐶 = 1 2 × 3 . 1316 × √200𝑢𝑢 × 100𝑢𝑢 1.1 KHz
Fig-7: output voltage for 50ms. 8. The new voltage overshoot is approximately 35.34 V and ripple voltage of the output is 0.76V .
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