LabReport3_COEN212_AnasSenouci_40132281

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Concordia University *

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212

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Electrical Engineering

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Jan 9, 2024

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LAB REPORT III COEN 212 Digital Systems Design I Lab Section: ECAX Experiment #3: Design of (Medium Scale Integration) MSI Components Anas Senouci ID: 40132281 Lab Instructor: Afrasiabi Negar Date Performed: May 30, 2022 Date Due: June 6, 2022 I certify that this submission is my original work and meets the Faculty’s Expectations of Originality. Anas Senouci June 6, 2022
OBJECTIVES The objective of this experiment is to become familiar with word-sized versus single bit operands and to design combinational adder circuit. More precisely, the goal is to design and verify a multiplexer, a half, and a full adder circuit. THEORY It is important to understand the three main components studied in lab. The first one being the multiplexer (or mux) is a device that allows the selection of a certain input to route to the input. The Figure 1 shows how the switch from input to input is made. Secondly, the half-adder is a device that can add two single binary digits and provide the output plus a carry value. The Figure 2 shows the circuit in the component. Finally, the full-adder is a component that can add three one-bit binary numbers, two operand and a carry bit, it is designed to be able to take eight inputs to create a byte-wide adder. The Figure 3 shows a 3-bit ripple-carry adder. Figure 2: Circuit of a half adder Figure 1: Operation of a 4-to-1 mux by means of a switch analogy Figure 3: A3-bit ripple-carry adder
RESULTS Multiplexer Table I. 2-1 multiplexer truth table S IN0 IN1 OUT 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 Table II. 2-1 multiplexer truth table IN0, IN1 S 00 01 11 10 0 0 0 1 1 1 0 1 1 0 Expression (SOP): P 1 = S IN1 + S IN2 1 IN1 2 7408 3 OUT 3 1 2 7432 2 4 6 5 7408 1 IN0 7404 S 2 1 0 Figure 4 : Multiplexer circuit
Half-adder Table III. Half-adder truth table A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 Expression (SOP): Sum = A’B + AB’ = A B Carry = AB Full-adder Table IV. Full-adder truth table A B C in S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Table V. Sum(A,B,C in ) k-map 1 0 3 A Sum 1 2 7486 B 1 Carry 3 2 7408 Figure 5: Half adder circuit
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