ECE 2020 HW3 Solutions

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1 ECE 2020 IE-1 Spring 2023 Homework 3 - Solutions Assigned: Thursday, 23 February, 2023 Due: Sunday, 05 March 2023, 11:59 PM (ET) Total Points: 6 questions, 100 points SHOW SUFFICIENT EXPLANATION OR WORKING STEPS FOR YOUR ANSWERS. I CANNOT PROVIDE COMPLETION CREDIT IF YOU ARE NOT SHOWING WORKING STEPS. QUESTION 1 ( 8 + 4 = 12 points) (a) An engineer implements the following switching circuit using normally-open and normally-closed switches. Draw truth tables and write the Boolean expressions for the circuit function for the following logic conventions: i. Both inputs & outputs use positive-logic. ii. Input positive-logic, output negative-logic. iii. Inputs negative-logic, output positive-logic. iv. Both inputs & output use negative-logic. Note: The ‘squiggly’ bit that connects Y to ground is a resistor. Don’t worry about this— Just take it to mean that if there’s no path from ‘ HI ’ to Y , then Y is equal to ‘ GND ’ (ground). (b) An engineer creates the circuit shown to the right side, with a bulb, switch, resistor. and two 5V batteries. The switch, ‘A’ is an electronically-controlled switch that gets a voltage from another circuit that isn’t shown here. If ‘A’ receives a voltage of 5V, it closes. If it receives a voltage < 1 V, it is open. The resistor prevents a short circuit in the circuit. If there is no voltage on the side of the resistor near the switch, it passes a value of 0 V to the bulb's left terminal. If the switch, A is closed, the 5V battery on the left side is connected to the bulb's left side terminal. If the voltage difference between the bulb's terminals is 5 V, the bulb lights up. If the voltage difference is lower than that, the bulb is off. • If we use positive logic on both input and output, what kind of a Boolean circuit has the engineer created here? Explain your answer? • What Boolean function does it implement if we instead use negative logic on the input & positive logic on the output?

2 SOLUTIONS (a) Recall that positive logic implies that a ‘LO’ voltage / signal level is mapped to logic ‘0’, and a ‘HI’ voltage / signal is mapped to logic ‘1’. Negative logic convention has the opposite mapping (‘LO’ = ‘1’, ‘HI’ = ‘0’). Based on this, if we assume that normally-open switches close when a high voltage is applied, and normally-closed switches open due to a high voltage, we can generate the following output table for the switching network, with the signals marked as shown: i. Inputs & Output use positive logic: By inspection, we see that the function implemented by this switch circuit when both inputs and outputs use positive logic is: 𝒀𝒀 = 𝑨𝑨𝑩𝑩 ′ + 𝑩𝑩𝑩𝑩 + 𝑫𝑫 ′ ii. Inputs use positive Logic, Output uses negative logic: When the output uses negative logic, but the inputs use positive logic, the output is the complement of this function, i.e. 𝑌𝑌 ′ = 𝐴𝐴𝐵𝐵 ′ + 𝐵𝐵𝐵𝐵 + 𝐷𝐷 ′ ⟹ 𝑌𝑌 = ( 𝐴𝐴𝐵𝐵 ′ + 𝐵𝐵𝐵𝐵 + 𝐷𝐷 ′ ) ′ = ( 𝐴𝐴𝐵𝐵 ′ ) ′ ⋅ ( 𝐵𝐵𝐵𝐵 ) ′ ⋅ 𝐷𝐷 𝒀𝒀 = ( 𝑨𝑨 ′ + 𝑩𝑩 ) ⋅ ( 𝑩𝑩 ′ + 𝑩𝑩 ′ ) ⋅ 𝑫𝑫 iii. Inputs use negative Logic, Output uses positive logic: The effect of implementing negative logic at the inputs means that the switches work opposite to ‘normal’ functioning (by ‘normal’, I mean positive logic, since that is the intuition that we’re most familiar with). This has the effect of complementing each of the inputs. If the output is positive logic, then we have 𝒀𝒀 = 𝑨𝑨 ′ 𝑩𝑩 + 𝑩𝑩 ′ 𝑩𝑩 ′ + 𝑫𝑫 iv. Inputs & Output use negative logic: And if the output is also negative logic, we get 𝑌𝑌 = ( 𝐴𝐴 ′ 𝐵𝐵 + 𝐵𝐵 ′ 𝐵𝐵 ′ + 𝐷𝐷 ) ′ ⟹ 𝑌𝑌 = ( 𝐴𝐴 ′ 𝐵𝐵 ) ′ ⋅ ( 𝐵𝐵 ′ 𝐵𝐵 ′ ) ′ ⋅ 𝐷𝐷 ′ 𝒀𝒀 = ( 𝑨𝑨 + 𝑩𝑩 ′ ) ⋅ ( 𝑩𝑩 + 𝑩𝑩 ) ⋅ 𝑫𝑫 ′

3 We could also demonstrate this more explicitly using a truth table. We first start by creating an output table for the switch network, which is independent of any logic convention : Voltages @ Switches Connections Voltage @ Y A B C D (1) = BC (2) = AB’ (3) = D’ LO LO LO LO No No Yes HI LO LO LO HI No No No GND LO LO HI LO No No Yes HI LO LO HI HI No No No GND LO HI LO LO No No Yes HI LO HI LO HI No No No GND LO HI HI LO Yes No Yes HI LO HI HI HI Yes No No HI HI LO LO LO No Yes Yes HI HI LO LO HI No Yes No HI HI LO HI LO No Yes Yes HI HI LO HI HI No Yes No HI HI HI LO LO No No Yes HI HI HI LO HI No No No GND HI HI HI LO Yes No Yes HI HI HI HI HI Yes No No HI Thereafter, we can map these voltages to the logic levels according to the logic convention. With this in mind, we can create truth tables for the different functions. First, we create the truth table for the inputs with positive-logic convention: (Positive-logic) Inputs Output, Y A B C D Voltage Positive Logic Negative Logic 0 0 0 0 HI 1 0 0 0 0 1 GND 0 1 0 0 1 0 HI 1 0 0 0 1 1 GND 0 1 0 1 0 0 HI 1 0 0 1 0 1 GND 0 1 0 1 1 0 HI 1 0 0 1 1 1 HI 1 0 1 0 0 0 HI 1 0 1 0 0 1 HI 1 0 1 0 1 0 HI 1 0 1 0 1 1 HI 1 0 1 1 0 0 HI 1 0 1 1 0 1 GND 0 1 1 1 1 0 HI 1 0 1 1 1 1 HI 1 0

4 And for negative logic, we get the reversed truth table: (Negative-logic) Inputs Output, Y A B C D Voltage Positive Logic Negative Logic 1 1 1 1 HI 1 0 1 1 1 0 GND 0 1 1 1 0 1 HI 1 0 1 1 0 0 GND 0 1 1 0 1 1 HI 1 0 1 0 1 0 GND 0 1 1 0 0 1 HI 1 0 1 0 0 0 HI 1 0 0 1 1 1 HI 1 0 0 1 1 0 HI 1 0 0 1 0 1 HI 1 0 0 1 0 0 HI 1 0 0 0 1 1 HI 1 0 0 0 1 0 GND 0 1 0 0 0 1 HI 1 0 0 0 0 0 HI 1 0 (b) The basic version of this question has been included and answered in the switching logic practice quiz posted on canvas, but I’ll expand on the solution here. If we look at the behaviour of the circuit when switch A is open or closed, we see that when switch A is open, as explained in the question, the voltage at the bulb’s left terminal is 0 V, i.e. ‘LOW’. When the switch A is closed, the voltage at this terminal is 5V, since there is now a connection between the left battery and the bulb’s lead. Notice that in both cases, the voltage at the bulb’s right terminal stays at 5V, because the right side battery stays connected to the bulb. We can then create a table of the voltage values: Switch A Voltages on Bulb’s terminals Bulb output Behaviour +ve logic -ve logic Left Right Difference Behaviour Boolean (+ve logic) Open 0 1 0 V 5 V 5 V ON 1 Closed 1 0 5 V 5 V 0 V OFF 0 Clearly, we can see that when the input is positive logic, and the output too is positive logic, the circuit acts as an inverter. When the input changes to negative logic, with the output remaining positive logic, the circuit acts as a buffer.

5 QUESTION 2 (4 + 4 + 4 + 6 + 7 = 25 points) Implement the following Boolean functions using either CMOS logic or with switching circuits that— unless specified—use only uncomplemented variables (i.e., use normally-open & closed switches). Ensure that the network has paths from both 0 (Vdd) and 1 (Ground) to the output. This requires you to create both a ‘pull-up’ circuit made of switches, and a pull-down circuit. You need to show circuit for these Boolean functions with both the pull-up and pull-down networks. (a) 𝑌𝑌 = ( 𝐴𝐴 + 𝐵𝐵 ′ + 𝐵𝐵 ) ⋅ ( 𝐵𝐵 + 𝐵𝐵 ′ ) (b) 𝐹𝐹 = 𝐴𝐴𝐵𝐵 ′ + 𝐵𝐵𝐵𝐵𝐸𝐸 ′ + ( 𝐴𝐴𝐷𝐷 ) ′ with a tri-state enable input, 𝐸𝐸𝐸𝐸 (c) 4-input OR gate (d) A 2-input XOR gate, with both the pull-up and pull-down networks implemented in PoS form. For part (e), you can use either uncomplemented or complemented literals. However, you are constrained in the types of switches you can use: (e) 𝐹𝐹 = 𝐴𝐴 ′ 𝐵𝐵 + 𝐴𝐴𝐵𝐵𝐷𝐷 ′ + 𝐵𝐵 ′ 𝐷𝐷′ . For the pull-up network, use only normally-closed switches. For the pull-down network, use only normally-open switches. SOLUTIONS The solution using CMOS logic is: (a) 𝒀𝒀 = ( 𝑨𝑨 + 𝑩𝑩 ′ + 𝑩𝑩 ) ⋅ ( 𝑩𝑩 + 𝑩𝑩 ′ ) (b) 𝑭𝑭 = 𝑨𝑨𝑩𝑩 ′ + 𝑩𝑩𝑩𝑩𝑬𝑬 ′ + ( 𝑨𝑨𝑫𝑫 ) ′ with a tri- state enable input, 𝑬𝑬𝑬𝑬 (the tri-state circuit is shown in blue) 𝐹𝐹 = 𝐴𝐴𝐵𝐵 ′ + 𝐵𝐵𝐵𝐵𝐸𝐸 ′ + ( 𝐴𝐴𝐷𝐷 ) ′ = 𝐴𝐴𝐵𝐵 ′ + 𝐵𝐵𝐵𝐵𝐸𝐸 ′ + 𝐴𝐴 ′ + 𝐷𝐷 ′

6 And the solution using switching logic equivalents with uncomplemented variables is: (a) 𝒀𝒀 = ( 𝑨𝑨 + 𝑩𝑩 ′ + 𝑩𝑩 ) ⋅ ( 𝑩𝑩 + 𝑩𝑩 ′ ) (b) 𝑭𝑭 = 𝑨𝑨𝑩𝑩 ′ + 𝑩𝑩𝑩𝑩𝑬𝑬 ′ + ( 𝑨𝑨𝑫𝑫 ) ′ with a tri- state enable input, 𝑬𝑬𝑬𝑬 (shown in blue) PUN = ( 𝑨𝑨 + 𝑩𝑩 ′ + 𝑩𝑩 ) ⋅ ( 𝑩𝑩 + 𝑩𝑩 ′ ) PDN = � ( 𝑨𝑨 + 𝑩𝑩 ′ + 𝑩𝑩 ) ⋅ ( 𝑩𝑩 + 𝑩𝑩 ′ ) � ′ = 𝑨𝑨 ′ 𝑩𝑩𝑩𝑩 ′ + 𝑩𝑩 ′ 𝑩𝑩 PUN = 𝑭𝑭 = 𝐴𝐴𝐵𝐵 ′ + 𝐵𝐵𝐵𝐵𝐸𝐸 ′ + 𝐴𝐴 ′ + 𝐷𝐷 ′ PDN = 𝑭𝑭 ′ = ( 𝑨𝑨 ′ + 𝑩𝑩 )( 𝑩𝑩 ′ + 𝑩𝑩 ′ + 𝑬𝑬 ) 𝑨𝑨𝑫𝑫 (c) 4-input OR gate We can implement this in two ways, either inverting each of the inputs in the pull-up network, or by first creating a NOR gate followed by an inverter at the output. I will show both implementations. PUN for NOR gate: ( 𝑨𝑨 + 𝑩𝑩 + 𝑩𝑩 + 𝑫𝑫 ) ′ = 𝑨𝑨 ′ 𝑩𝑩 ′ 𝑩𝑩 ′ 𝑫𝑫 ′ PDN for NOR gate: ( 𝑨𝑨 + 𝑩𝑩 + 𝑩𝑩 + 𝑫𝑫 ) ′ ′ = 𝑨𝑨 + 𝑩𝑩 + 𝑩𝑩 + 𝑫𝑫

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