1. (25%) Compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI = 1 Processor without cache: Assume main memory access time of 4 cycles Assume 50 % instructions require memory data access Processor with cache: Assume cache access time of 1 cycle Assume hit rate 0.95 for instructions, 0.80 for data

1. (25%) Compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI = 1 Processor without cache: Assume main memory access time of 4 cycles Assume 50 % instructions require memory data access Processor with cache: Assume cache access time of 1 cycle Assume hit rate 0.95 for instructions, 0.80 for data

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

(15pt) Assume that instruction cache miss rate is 2%, data cache miss rate is 10%, CPI (clock cycle per instruction) is 2 without any memory stall, and miss penalty is 100 cycles. In addition, assume that the frequency of loads/stores is 30%. (a) Compute CPI with memory stall. (b) When CPI without any memory stall becomes 1, compute CPI with memory stall. (c) If the CPU clock rate is doubled with the same memory when CPI without memory stall is 2, compute CPI with memory stall.
Consider a two-level memory system (i.e., cache and main memory). Assume the cache access time is 3 clock cycles, and the hit rate is 95%. What should be the main memory access time (penalty) to ensure the memory access efficiency stays at 0.90?
Problem: Assume a computer design problem having following parameters:Main memory: 128KB, 4-way Set-Associative mapped cache, Cache size: 1KB,Block size: 8 Bytes. Computer program accesses (in order) memory locations:137, 138, 169, 170, 1203, 1205.(i) What is the hit ratio?(ii) What are the final cache contents?Assume that the cache is empty at the beginning.
a.What is the cost of 1 MB of main memory? b.What is the cost of 1 MB of main memory using cache memory technology? c.If the effective access time is 10% greater than the cache access time, what is the hit ratio H?
Note:- Don't copy paste and existing Answers will downvote Sub:- Computer Architecture Assume the cache miss penalty is 100 clock cycles and all instructions normally take 1.0 clock cycles (ignoring memory stalls). Assume the average miss rate is 2%, there is an average of 1.5 memory references for instruction, and the average number of cache misses per 1000 instructions is 30. What is the impact on performance when behavior of the cache is included? Calculate the impact using both misses per instruc tion and miss rate.
1. Develop a mathematical model for measuring performance based on overall memory access time with a neat diagram for the following memory design and derive the formula to calculate the Overall Memory Access Time. Main Memory : 1 Internal Cache : 1 External Cache: 1 Register S and Register B have fastest access time: Data Search order [ Registers – Internal Cache – External Cache – Memory] [Hint: Register access time is considered negligible]
Q3 If a microprocessor has L1 and L2 caches. The access time for L1 cache is τ. The miss penalties for transferring a block of memory from L2 to L1 is 10τ and it takes 120τ for transferring a block from memory to L2. The hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.90 and 0.85, repectively. I. Determine the fraction of accesses miss in both the L1 and L2 caches, thus requiring access to the main memory? II. What is the average access time as seen by the processor? Q4 Determine the number of bytes included in the address ranging from 123000H to 0C37000H, you must present the answers using units of Mbytes, Kbytes and bytes. Q5 If the size of a program is 424892 Bytes and its starting address is 000000H, determine the ending address of the program.
Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.
Assume for arithmetic, load/store, and branch instructions, a processor has CPIs for 1, 12, and 5respectively. Also assume that on a single processor a program requires the execution of 2.56*10^9arithmetic instructions, 1.28*10^9 load/store instructions, and 256 million branch instructions. Assumethat each processor has a 2GHz clock frequency. Assume that, as the program is parallelized to run overmultiple cores, the number of arithmetic and load/store instruction per processor is divided by 0.7xp(where p is the number of processors) but the number of branch instructions per processor remains thesame. a- Find the total execution time for the program on 1,2,4, and 8 processors, and show the relativespeedup of the 2,4, and 8 processor result relative to single processor result. b- If the CPI of the arithmetic instruction was doubled, what would be the impact be on theexecution time of the program on 1,2,4, and 8 processors? c- To what should the CPI of load/store instructions be…
Section 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.
Assume the following performance characteristics on a cache read miss: one clock cycle to access cache memory, one clock cycle to access main memory, and six clock cycles to transfer a 32-bit word to the processor and cache. If the cache line size is one word, the miss penalty will be 1+1+6 = 8.0. Given this information: A. What is the miss penalty if the cache line size is four words and a multiple, nonburst transfer is executed? B. What is the miss penalty if the cache line size is four words and a transfer is executed, with one clock cycle per word transfer?
For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes, Direct mapped cache.Calculate the Hit ratio while CPU runs program “Test_Cache”. Also count how many blocks arereplaced in cache memory assuming the cache is empty at the beginning.For the same RAM, block size and Cache memory, what would be the Hit ration in case of FullyAssociative Mapping?For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way SetAssociative Mapping?Main Program—“Test_Cache”