1.4 Compute 8 + 12 using the binary adder using the binary adder logic symbol. Draw an image of the logic symbol, and label the appropriate inputs and outputs with a 1 or a 0.

A B C D HO [ E E E F F D G F G D 1. Simulate the circuit and built the truth table using the following headers. Truth Table 1 OUTPUT INPUT C A B E F D D G 0 X 1 --X

1| Rev 001 Eff Date: 09-08-2023 QP-ASR-001 | Rev 001 Eff Date (b) Draw a logic circuit diagram of the following Boolean expression: i. AB+C+ACB+B ii. ABC + ABC + AC (c) Convert the following expression to sum-of-product form F(A, B, C) AB + BC + AC Question 3: [Total Marks: 10] [5 marks] [5 marks] [5 marks] (a) Draw the logic circuit diagram for the following Boolean expressions using only NAND Gates X= AB (b) Draw the logic circuit diagram for the following Boolean expressions using only NOR Gates X=AB Question 4: [Total Marks: 10] (a) What is the Control word for the following micro-operations? [6 marks] i. R1 <- R2 + R3 ii. R2 <- SHR R2 Page 2 of 3 iii. R7 <- R2-R3 (b) The following instructions are performed in a processor based on general register organization. If R1 = 1001 and R2 = 1101, what will be the value of register R2 in the following operations: i. R2 <- SHR R2 ii. R2 <- R2 + R1 [4 marks] Question 5: [Total Marks: 15] Given the expression (A+B)*(C-D)+(E/F*G) (a) Find the…

3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description: (a) module Circuit_A (A, B, C, D, F); input output A, B, C. D: F; w, x, y, z, a, d; (x, B, C, d); (v, a .C): wire or and (y, a ,C); (w. z B): and and (z, y, A); (F, x, w); (a, A); (d, D); endmodule or not not (b) module Circuit_B (F1, F2, F3, A0, A1, BO, B1); F1, F2, F3; output input A0, A1, B0, B1; (F1, F2, F3); (F2, w1, w2, w3); (F3, w4, w5): (PS, W4, (w1, w6, B1); nor or and and (w2, w6, w7, B0); (w3, w7, B0, B1); or and (w6, A1); (w7, A0): not not (w4, A1, B1); (w5, A0, BO); xor xnor endmodule (c) module Circuit_C (y1, y2, y3, a, b); output y1, y2, y3; input a, b; assign y1 = a || b; and (y2, a, b); assign y3 = a && b: endmodule