4. In this question, we consider the relative performance obtained by running a particular program with various caches installed between the memory and the CPU. Consider the following C function: 1 char a [512], b[512] 3 add arrays () { register int i; for (i = 0; i < 511; i = i+1) { a[i+1] = a[i] + b[i]; // Work!! (The register keyword tells the C compiler to reserve a register for the variable it keeps i in RO. What does this mean for us? The variable i is not stored in main memory- it's stored in the CPU; this mean that it never has to be pulled from main memory into the cache when the CPU accesses it. let's assume The char keyword allocates character arrays at fixed locations in memory, using 1 byte per character.) Recall that in C, an array is a contiguous chunk of memory. Therefore, in this code, array a starts at some address (say, 0x00A), and ends at (start address) +n-sizeof (char) address, where n is the number of elements and sizeof (char) is the number of bytes a char takes in memory (and in this example, we're using char because it's 1 byte and makes calculating simple!). For the following questions, assume that the memory can read or write 1 byte at a time.

4. In this question, we consider the relative performance obtained by running a particular program with various caches installed between the memory and the CPU. Consider the following C function: 1 char a [512], b[512] 3 add arrays () { register int i; for (i = 0; i < 511; i = i+1) { a[i+1] = a[i] + b[i]; // Work!! (The register keyword tells the C compiler to reserve a register for the variable it keeps i in RO. What does this mean for us? The variable i is not stored in main memory- it's stored in the CPU; this mean that it never has to be pulled from main memory into the cache when the CPU accesses it. let's assume The char keyword allocates character arrays at fixed locations in memory, using 1 byte per character.) Recall that in C, an array is a contiguous chunk of memory. Therefore, in this code, array a starts at some address (say, 0x00A), and ends at (start address) +n-sizeof (char) address, where n is the number of elements and sizeof (char) is the number of bytes a char takes in memory (and in this example, we're using char because it's 1 byte and makes calculating simple!). For the following questions, assume that the memory can read or write 1 byte at a time.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose we have the following parameters on a two level cache system (L1 is closer to CPU). L1 Cache: Size = 4Kbytes Hit rate: 1 cycle Miss rate: 0.10 misses per memory reference Miss penalty: 3 cycles if found in L2 cache L2 Cache: Size = 64Kbytes Miss rate: 0.02 misses per memory reference Miss penalty: 10 cycles Assume that 20% of all instructions reference memory (i.e., load and store). What is the CPI of this processor (In a perfect cache system, each instruction takes 1 cycle)?
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
The following code, written in C, where elements within the same row are stored contiguously, was implemented on a computer system containing the cache system already discussed.for( i = 0; i < 8; i++ )for( j = 0; j<8000; j++ )a[i][j] = b[i][0] + a[j][i]a) References to which variables exhibit temporal locality?b) References to which variables exhibit spatial locality? (please explain in details)
Suppose that immediately following the two read operations of question 1,the program does read operations on the following memory addresses (e.g., with “lb”or “lw” instructions): 148, 224, 556, 248 (again), 6728, 1312 (again), and 128.Assuming the cache was empty prior to the read operations of question 1, state whichof these read operations will result in cache hits, assuming a 2-way set-associativecache with a total capacity of 4 eight-word blocks and LRU replacement in each set. Suppose that a program does read operations on the following memory addresses (e.g., with “lb” or “lw” instructions): 248, 1312. Give the number of the memory block that each of these addresses belongs to, for each of the following memory block sizes. A. block size of one word (4 bytes) B. block size of eight words (32 bytes) just do the first part
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
17. a) Consider an application running on a multiprocessor system that takes 600 cycles,(during which processors are stalled), to handle a local cache miss leading to referencing a remote memory. The CPI for all references that hit in cache is 1 cycle. If 0.2% of cache access result in a local miss, how much faster will the system run if it has a perfect cache that never miss.
Now, we consider a 16-byte, four-way, fully-associative cache. Since the capacity of the cache is 16 bytes, the array "a" in our example (does/does not) fit inside the cache. We can deduce that the block size for this cache is ( ？ ) bytes per block. So the block index size b=2 bits. For a memory trace record such as: L 1fff000116,2 the 2-bit block offset is (0b01/0b10/0b11/0b00). The tag bits are all the rest of the bits not part of the block offset.
The following table gives the parameters for a number of differentcaches. Your task is to fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits.
Consider the following list of memory address references. These memory accesses are cached in a cache that has 8 blocks where each block size is two words (2 x 4 bytes). The cache uses direct mapped placement. 0x03, 0xb4, 0x2b, 0x02, 0xbf, 0x58, 0xbe, 0x0e, 0xb5, 0x2c, 0xba, 0xfd a. For each of these references, identify the tag and index field values. b. For each of the references above, identify if each reference is a hit or a miss, assuming the cache is initially empty.
In this exercise, we will look at the diff erent ways capacity aff ects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. Th e following table shows data for L1 caches attached to each of two processors, P1 and P2. L1 Size L1 Miss Rate L1 Hit Time P1 2 KiB 8.0% 0.66 ns P2 4 KiB 6.0% 0.90 ns Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? What is the Average Memory Access Time for P1 and P2? Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
Consider a cache with the following parameters: N (associativity) = 2, b (block size) = 2 words, W (word size) = 32 bits,C (cache size) = 32 K words, A (address size) = 32 bits. You need consider only word addresses.(a) Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each field.(b) What is the size of all the cache tags in bits?(c) Suppose each cache block also has a valid bit (V) and a dirty bit (D). What is the size of each cache set, including data, tag, and status bits?(d) Design the cache using the building blocks in Figure 8.28 and a small number of two-input logic gates. The cache design must include tag storage, data storage, address comparison, data output selection, and any other parts you feel are relevant. Note that the multiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K × 4 bits. Be sure to include a neatly labeled block diagram. You need only design the…
As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table (a) For each access shown above, list whether the access is a hit or miss in the TLB, whether the access is a hit or miss in the page table, whether the access is a page fault, the updated state of the TLB. (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages? (c) Repeat Part a, but this time use 4 KiB pages and a two-way set associative TLB. (d) Repeat Part a, but…