´ou are evaluating its cache performance on a machine with a 1024 -byte direct-mapped data 16-byte blocks (B=16). Assume the sizeof(int) = 4 , x and y are variables defined in a struct is at memory address 0 ,the cache is initially empty and the only memory accesses are to the ne array grid. For the following code: the total no.of reads? the total no.of reads that miss in the cache? = the miss rate? for (i = 0; i< 16; i++) { for (j = 0; j< 16; jt#) { total x += grid[].x: total y += grid[j](lL.v; }}

´ou are evaluating its cache performance on a machine with a 1024 -byte direct-mapped data 16-byte blocks (B=16). Assume the sizeof(int) = 4 , x and y are variables defined in a struct is at memory address 0 ,the cache is initially empty and the only memory accesses are to the ne array grid. For the following code: the total no.of reads? the total no.of reads that miss in the cache? = the miss rate? for (i = 0; i< 16; i++) { for (j = 0; j< 16; jt#) { total x += grid[].x: total y += grid[j](lL.v; }}

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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For the following loop, assume the array arr2[][] has never been referenced before in the code. Also assume that a cache line is 32 Bytes, and an int is 4 Bytes. 1. How many memory references are there?2. How many cache misses are there?
For the following loop assume the array arr2[][] has never been referenced before in the code. Also assume that a cache line is 32 Bytes, and an int is 4 Bytes. 1. How many cache misses are there?
Q5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. What is the total number of data cache misses (including compulsory misses) when running the above code?
Q5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. Assume we change the cache configuration to be 2-way set-associative. This new data cache has 8 sets and 16 bytes per line. The cache uses a Least Recently Used (LRU) replacement policy. How many data cache misses (including…
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instruction is in the first picture please give me only implementation of int L1lookup(u_int32_t address) and int L2lookup(u_int32_t address) cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0…
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