A combinational circuit is defined by the following three Boolean functions. Implement the circuit with a decoder constructed with NAND gates and external NAND gates. F1 (A, B, C) = Em(0, 5, 7) F2(A, B, C) = Em(2, 3, 4) F3 (A, B, C) = Em(1, 6, 7) %3D 3x8 Decoder mo m1 A m2 m3 m4 m5 m6 m7

The truth table for a Boolean expression is shown on figure1.  A, B, C, D are inputs and Y is the output Write the Boolean expression on SOP form Y = f (A, B, C, D) Minimize the function using Karnaugh Map (K Map) Draw the minimized function using logic gates

1. A. Convert A5Q(27)→ X(9) 2. Simplify the Karnaugh maps and draw the logic circuit. AB 00 01 11 10 CD 00 1 1 1 1 01 1 1 11 1 1 10 1 1 11 1 AB 00 01 11 10 CD 00 1 1 01 11 1 1 10 11 11 1 1

A combinational circuit is described by this Boolean Expression: F(A,B,C,D) = 2m(0,2,4,8,9) i) Minimise the Boolean Expression given above using a Karnaugh map. ii) Given Don't Care conditions d = Em (10,11,12), use a separate Karnaugh map to demonstrate how you would further simplify the expression in part i). iii) Use Switching Algebra to show how you would implement the function obtained in part ii) by using NAND gates only. Provide a circuit diagram in your answer. Show all your working.

The output of a combinational circuit which implements a majority function F(x,y,z) is equal to 1 if more input variables are equal to 1 rather than 0. The output is O otherwise, e.g. F(1,1,0)=1, F(0,0,1)=0. Which of the following expressions represent the simplified expression for function F? F = xy + xz + yz OF= xz + xy F = x + zy + z OF = x e y e z

Implement the diagram in part b and verify its function experimentally by constructing a truth table from the test data.

Draw the truth tables for the following Boolean expressions. xy+yz+xz x¯y+yz¯+x¯z (x⊕y)+(y⊕z)+(x⊕z) (xy)¯⊕ z 2.Draw circuit diagrams implementing each of the above expressions. You may simplify the expressions or not, as you choose. You may use any of the six fundamental logic gates (AND, OR, NOT, NAND, NOR and XOR). I need help on question 2 containing the circuit diagrams

Given the following functions, F(A, B, C) = Em(0, 4, 6, 7) G(A, B, C) = [IM(1, 2, 3,4, 7) a. Implement both functions using a PROM chip (draw full grid) b. Implement both functions using as many 2:4 decoders chips (with a single active low enable) and any other logic gates needed in one circuit.

1- In the following sequential circuit. There are 2 D FF (A and B), 2 inputs (x and y), and 1 output z The output and next-states equations are given A(t+1) = x'y + xA B(t+1) = x'B + xA z=B b- List the state table for the sequential circuit.