(a) Consider the Binary Coded Decimal-to- Decimal Decoder (implemented with NAND gate) shown in Figure below. The figure shows the timing for the inputs (Ao. A1, A2, and A3). Draw the timing for the outputs considering the relationship with each other's and with inputs. BCD/DEC Ag A A2 Ay 74HC42

Given: In a Laser Circuit FSM, the output x equals 25 nanoseconds, and Tclk equals 5 nanoseconds. Question: Write VHDL code showing separate “blocks” for the next state decoder, memory, and output decoder. Add an Asynchronous Reset active Low.

Design a 2-bit modulo 8 synchronous counter in Multisim and implement the design using two 74LS112 IC JK flip flops based on this circuit. Use word generator and logic analizer as shown.

please find F= and thanks for your help