A modern computer central processing unit chip (CPU) runs with a clock speed of 2.7 GHz. It can execute one operation in each of these clock cycles. a. How many seconds long is one clock cycle? b. Electrical signals travel at the speed of light. How far can an electrical signal travel in one clock cycle? c. Wires between the CPU's control unit and its cache memory (both on this chip), are about 2 cm long. How does this compare to how far an electrical signal can travel in one clock cycle?

A modern computer central processing unit chip (CPU) runs with a clock speed of 2.7 GHz. It can execute one operation in each of these clock cycles. a. How many seconds long is one clock cycle? b. Electrical signals travel at the speed of light. How far can an electrical signal travel in one clock cycle? c. Wires between the CPU's control unit and its cache memory (both on this chip), are about 2 cm long. How does this compare to how far an electrical signal can travel in one clock cycle?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
Consider a CPU that operates with a data transfer rate of 30 Mbytes/s. The data is transferred byte-wise and the CPU has to transfer 30bytes of data, and the size of the Status register is 4 bytes. What is the total time needed to perform the data transfer?
On a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
3. If we have an 8 bit microcontroller that has 4kB of instruction memory starting at address 0x0000, and 2kB of data memory immediately above that, what is the next available byte in our address map?
Let's pretend for a moment that we have a byte-addressable computer with 16-bit main memory addresses and 32-bit cache memory blocks, and that it employs two-way set associative mapping. Knowing that each block has eight bytes, please calculate the size of the offset field and provide evidence of your calculations.
5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. (a) Suppose all instructions and operands are one byte long, by what factor do the maximum data transfer rates differ?
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. Which processor has the highest performance expressed in instructions per second? If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions.
Suppose a given processor has access to two levels of memory. Level 1 contains 1000 words and has an access time of 0.01 μs; level 2 contains 100,000 words and has an access time of 0.1 μs. Assume that if a word to be accessed is in level 1, then the processor accesses it directly. If it is in level 2, then the word is first transferred to level 1 and then accessed by the processor. For simplicity, ignore the time required for the processor to determine whether the word is in level 1 or level 2. Suppose 95% of the memory accesses are found in level 1, define the hit ratio (H) and find the average access time.
Suppose two CPU A and B have exactly the same circuits, but different clock frequencies. Answer the following questions: a) If the clock frequency of CPU A is 8MHz, how long is one clock cycle of CPU A? b) If the CPU A can execute 0.4 million instructions per second on average, how long is the average time to execute one instruction? c) What is the average number of clock cycle to execute one instruction for CPU A? d) The frequency of CPU B is 12MHz. What is the average number of instructions that can be executed per second?
Suppose that a microprocessor operates at 5MHz. How long does the bus cycle occupy, assuming no wait states are inserted?
In this problem, you will explore processor frequency in the context of the speed of light.Suppose you have overclocked a processor to 8,722.78MHz. This processor can execute one instruction per cycle. Further let us suppose that the system is accessing a magnetic disk (HD) with an access time of 11ms. 1. Suppose that you are designing the machine architecture and want to guarantee the CPU can obtain data from memory within 4 CPU cycles. Given that the address has to travel from the CPU to the memory unit (MMU) and that the data has to travel from memory to the CPU, what is the maximum distance between CPU and the MMU if the signal on the memory bus propagates at 75% of the speed of light?