6. A processor with 32 address bus could be interfaced with memory locations. a) 512 M c) 2048 M b) 1024 M d) 4096 M

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
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6. A processor with 32 address bus could be interfaced with
memory locations.
a) 512 M
c) 2048 M
b) 1024 M
d) 4096 M
Transcribed Image Text:6. A processor with 32 address bus could be interfaced with memory locations. a) 512 M c) 2048 M b) 1024 M d) 4096 M
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