A sequential circuit has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces z = 1; otherwise, z = 0. For example wi :0110111000110 w2 : 1110101000111 z : 0000100001110 Derive a suitable circuit.

In the given circuit, 7483 are additions and 7485 comparisons. Four-bit X and Y numbers are applied to the inputs of the circuit. In what situations would the output Q of this circuit be logic 1? A  X+Y<8 ise B  X+Y<7 ise C  X+Y>7 ise D  X+Y=8 ise E  X+Y>4 ise

Suppose r0=0x300010A0, r2 = 0x00000011, and the memory layout is as follows. Address Data 0x300010A7 0x72 0x300010A6 0xA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0xA5 0x300010A0 0x01 What is the value of 10 and r1 after executing LDR r1, [r0, #2]?

2)Convert 11011010100100012 to hexadecimal. A)895B B)CA11 C)53AC1 D)DA91