A VHDL component is called for use in a program by using a(a) signal (b) variable(c) component instantiation (d) architecture declaration

Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD LOGIC; Q: out STD LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0) ) & Q(5 downto 1); end if; end process; end behavior;

Given the these minterms (4, 5, 6, 7, 8, 9, 10, 13, 14, 15), write a VHDL STATEMAENT for the function as a SOP. Please use this Entity Declaration in formulating the statement entity midterm is Port(A, B, C, D in STD_LOGIC; F: out STD_LOGIC); end midterm;

One-dimensional systolic arrays vary from SIMD.

Digital logic

Design the following filter using filter design theory. LOW-PASS FILTER A low-pass filter is required to have a voltage gain of 1 in the pass band, to be 3 dB down at the cut-off frequency of 1.5 KHz and to be at least 80 dB down at 15 KHz. The design is to be a Butterworth filter using VCVS circuit (Sallen-Key).

show all the work

Design a deterministic finite-state automaton over the alphabet {a; b; c}that accepts words where each character is immediately followed by atleast one identical character. For example, it accepts the wordsY(gamma sigh), aa, aaa,aabbbbaacc, but it rejects the words a, baba, cbbba. Write the transition function of the automaton as a table and draw the automaton in the form of a transition diagram. Try to design the simplest possible automaton, i.e., an automaton with the smallest number of states.