Consider a system with 3 I/O devices •Printer (priority of 2) •Disk (priority of 4) •Communication line (priority of 5) User program begins at t = 0 and the multiple interrupts occur at following time instances •At t = 10, disk interrupt occurs •At t = 15, printer interrupts occurs •At t = 20 communication interrupt occurs Show the time sequence of multiple interrupts, assuming that service routine for each interrupt takes 10 time units.
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Consider a system with 3 I/O devices
•Printer (priority of 2)
•Disk (priority of 4)
•Communication line (priority of 5)
User
•At t = 10, disk interrupt occurs
•At t = 15, printer interrupts occurs
•At t = 20 communication interrupt occurs
Show the time sequence of multiple interrupts, assuming that service routine for each interrupt takes 10 time units.
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- You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, Show the address format for virtual address 0x12 (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. (Hint: Convert the address to its binary equivalent and divide it into the appropriate fields.) Explain how these fields are used to translate to the corresponding physical address.You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, Given virtual address 0x06 converts to physical address 0x36. Show the format for a physical address (specify the field names and sizes) that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache. (Hint: Convert 0x36 to binary and divide it into the appropriate fields.)You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, How many bits are in a physical address? Explain.
- A computer uses virtual memory, and a new solid-state drive (SSD) as space for paging. Refer to the last ppt file. In the case presented there, the hard disk drive (HDD) required 25 ms to read in a page, and a rate of 1 page fault per 1000 references introduced a 250 slowdown. If the SSD offers a time of only 80 µs, what is the slowdown in performance caused by 1 pf per 1000 references (you are not concerned with dirty vs. clean pages). What is the maximum rate of page faults you can accept if you want no more than a 5% slowdown in execution using virtual memory? Know your metric prefixes and symbols for time: s for seconds, ms for milliseconds, µs for microseconds, ns for nanoseconds.Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this case
- You have a virtual memory system with a two-entry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided up into blocks, where each block is represented by a letter. Two blocks equals one frame. A) Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame and what the physical address in binary? Explain your answers. B) Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers. C) Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s…Answer 4, 5 and 6 only !! ( NO PLAGARISM) Assume the following scenario for multi-level paging used by a process that has following: a. Logical Address = 64 bits b. Page size = 1 M Byte c. Page table entry size = 4 Byte d. System is byte addressable. calculate the following. 1. Logical Address Space? 2. Maximum number of page table entries in a single page? 3. How many levels of page table entries will be used? 4. Compute the size of page tables at each level? 5. Compute the number of entries in a single page? 6. Compute the number of pagesYou are given the following data about a virtual memory system:(a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 9 msec.If page references are handled by the TLB 99% of the time, and only 0.01%lead to a page fault, what is the effective address-translation time?
- Assume in a Virtual Memory system, a program needs 10 pages with page numbers 0 to 9 and each page is 4 words and the program is allocated 3 page frames: a, b, and c. The word trace for 26 memory accesses by the program are listed below. Use a table to compare the three replacement policies: LRU, OPTimal, and FIFO, by calculating and comparing the hit rate of each policy for these 26 memory accesses.Consider a demand-paged computer system where the degree of multiprogramming is currently fixed at seven. The system was recently measured to determine utilization of the CPU and the paging disk. Three alternative results are shown below. For each case, what is happening? Can the degree of multiprogramming be increased to increase the CPU utilization? Is the paging helping? Justify.a. CPU utilization 10 percent; disk utilization 95 percentb. CPU utilization 95 percent; disk utilization 1 percentc. CPU utilization 10 percent; disk utilization 5 percenConsider a swapping system in which memory consists of the following hole sizes inmemory order: 12 MB, 4 MB, 20 MB, 12 MB,18 MB, 7 MB, 9 MB and 12 MB.Which hole is taken for successive segment requests of(a) 10MB(b) 15MB(c) 9 MBfor first fit, worst fit, and next fit?