Construct a 16-bit serial-parallel counter, using four 4-bit parallel counters. Suppose that all added logic is AND gates and that serial connections are employed between the four counters. What is the maximum number of AND gates in a chain that a signal must propagate through in the 16-bit counter

Design a 3-bit counter which counts in the sequence: 001, 010, 110, 011, 111, 101, 100, (repeat) 001, ...

3. Design using copies of counter C and gates as needed to construct a counter with count sequence 24, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24.

Q1. Construct the truth table of a full adder which calculate [S, Cout] = A + B + Cin where A = A1Ao is a 2- bit number, B is a 1-bit number, Cin is a 1-bit carry-in S = SiSo is a 2-bit sum and Cout is a 1-bit carry-out, and implement its circuit using no more than 20 logic gates.

Implement a full adder using a 3-to-8 line decoder along with (a) two OR gates. (b) two NOR gates.

Consider a 5-bit right shift register each shifting data to the right for every clock pulse. The serial input A is derived by using NAND gates as shown in figure. If the initial content of the counter is 10001 at QOQ1Q2Q3Q4 by applying the clock signal then after how many clock pulse circuit is back to the initial state? Qo Q Q2 Q Q4 Register

The following circuit shows the carry-lookahead adder design. Assuming the delay for each gate is 2.2 ns, and there is no fan-in issue (meaning a gate can take as many inputs as possible). Consider a n-bit carry-lookahead adder, what is the duration (in ns) you have to wait until the correct C is generated? Carry-Lookahead Adder Ci+1=g; +pi ci = 8; + Pi (8-1 + Pi-1 C1.1) g+Pi8-1 + PiPi-11-1 = 81+Pi81-1+ Pi Pi-181-2+...+P1 Poco g₁ = xi yi Pi = x; + yi 2.2*(3+7*2) 2.2*3 2.2*8*n 2.2 n "

In verilog a counter must be developed from 0 to 9999 with a reset and parallel loading. The reset will be a button in charge of returning the count to 0 when pressed.For this practice, the implemented circuit will only use a 7-segment BCD converter module, which will have to be managed between the different 7-segment displays at a given frequency.

Question 4: Design and implement a minimal 5 modulo up counter. It counts from 0 to 4 and repeats. Design the circuit such that, if the counter enters into the unwanted states: 5, 6 and 7, it should jump into state 0 on the next clock pulse.

You have to design a fast multiplier: the operands are A1A0 and B1B0. Thendesign a fast adder for the same operands. Both circuits have to fit in the same IC;the operands are applied and the sum as well as the multiplication appear at theoutput. Obviously, your answer has to be correct AND economical.