Design a 512 MByte memory using 64M*4 chips, with 8-bit read/write operations and byte addressability.

Design a memory map for a system with 64 K of memory space, a 16-bit address bus, and a 8-bit data bus. The system needs to meet the following design requirements: The system needs 20 K of RAM, organized in a contiguous block starting at address 0x1000 . The system needs RAM filling the memory range from 0xA000 to 0xCFFF (inclusive) Your design must be subject to the following constraints in terms of access to memory chips: You can use a maximum of two (2) 8 K×8 RAM chips. You can use a maximum of two (2) 4 K×8 RAM chips. You can use a maximum of two (2) 8 K×8 ROM chips. You can use a maximum of two (2) 4 K×4 ROM chips.

Assume that a RISC processor takes 2 microseconds to execute each instruction and that an I/O device can wait at most 1 millisecond before its interrupt is serviced. What is the maximum number of instructions that can be executed with interrupts disabled?

In this section, please detail the amount of memory that can be addressed by the 20-bit address bus.