Design a Moore sequence recognizer that detects the Non-Overlapping sequence “101”. Use binary encoded state labels and design and draw the circuit schematic. (i.e. FSD, Next state generator Table (shows transition from current state to next state), Output Generator Table and schematic circuit. Please use output label as Y and input label

3. The truth table of the priority encoder has been given below: Inputs Outputs D3e D2 D1 D0 Ale A0- Ve 0 Xe Xe Xe Xe 3a. Draw the circuit diagram for this encoder by using simple logic gates (2-input 'and', 2-input 'or', and 'not' gates). 3b. Can you reduce the number of used logic gates by gate sharing? Give the number of used logic gates and draw the corresponding circuit. please provide detailed steps thanks Show transcribed image text 3. The truth table of the priority encoder has been given below: Inputs Outputs D32 D2 D14 DO A12 A02 ve T 02 02 O 02 Xe Xe 02 1 02 02 02 120 02 12 100 12 X 0 12 12 T. O 12 X X le 0 12 12 xe xe X2 12 12 12 2

Convert the function F = A' + B'C + BC'D' to а. a two-level NAND-NAND form b. a two-level NOR-OR form

you need to design and draw a 3-bit synchronous binary up/down counter for experiment 5. You need to add a bit named "M" for the excitation table that helps it switch between up and down mode and draw the state transition diagram, excitation table, k-map and circuit diagram with T-flip flops. When M = 0, it will perform up counter. When M = 1, it will perform down counter.