
Design a simple microprocessor called Custom-ARM which is a simple 16-bit single-cycle
processor that implements a custom instruction set.
The processor should consist of the following four main components:
- A register file
- An Arithmetic and Logic Unit (ALU)
- A read-only instruction memory (IMEM)
- A read/write data memory (DMEM)
This processor has 8 registers (R0-R7) and the program code is stored as 22-bit instructions in the IMEM. The processor implements three types of instructions, an instruction format example for 22-bit instructions is shown at Table 1. Some instruction examples are shown at Table 2.
A-) Design the instruction format for your 22-bit instructions for each type of instruction shown in Table 1. Different types of instructions with various parameter types (register and immediate) should be supported in your designs.
- Design four types of data processing instructions that are such as EOR, RSB, ADC, SBC, RSC, TST, TEQ, CMN, BIC, MVN, ...
- Design two types of memory instructions, one load and one store operation.
- Design two types of branch instructions, one B and one BL operation.
- See ARM-REFERENCE for more information about the instructions.
B-) Design your own ALU to support the instructions in your microprocessor more efficiently. You should add the four new data processing operations designed at step (a) to the ALU which implements ADD, SUB, AND and ORR operations. You can draw only the new additions/changes to the ALU
C-) Design and draw the datapath of the Custom-ARM processor by introducing connections to the components listed below. Show necessary control signals from the Control Unit.
Data Path Components:
Program Counter: One 16-bit register
Register File: 8 registers that hold 16-bit
Instruction Memory: 16-bit address input, and outputs 22-bit
Data Memory: 16-bit read/write memory
ALU: Performs arithmetic and logical operations
D-) Design the control unit of the Custom-ARM processor. The Control Unit generates necessary signals to the datapath. Show boolean functions for each signal at Main Decoder and ALU Decoder tables of the control unit. Check single-cycle ARM processor design in the lecture slides to design the signals such as MemToReg, MemWrite, RegWrite, ALUSrc, Branch …

![TABLE-2: Ege-ARM Instruction Examples
Instruction
Туре
Орсode/
Operation
Function
ADD rd,ra,rb
Data Processing
Memory
0001
rd = rd+rb
LDR rd, [rb]
0010
rd = DataMemory[rb]
B #imm9
Branch
0100
рс 3 рс + imm9](https://content.bartleby.com/qna-images/question/aea275d3-d8c1-45c8-bd96-504cb0395b52/a0fd9092-4e25-483b-8fc3-59613d0d78aa/lb0qi4l_thumbnail.png)

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- Orthogonality means that an instruction set has a "backup" instruction that can be used instead of any other instruction that does the same thing. It's up to you to prove or disprove what I think.arrow_forwardH.W.: Consider a hypothetical machine with two steps instruction cycle: fetch cycle and execute cycle. The characteristics of the machine is given in Figure 8 with the following explanation: The processor contains a single data register, called an accumulator (AC). • Both instructions and data are 8 bits long. • The memory is organized using 8-bit words. • The instruction format provides 2 bits for the opcode, and up to 26 = 64 words of memory can be directly addressed. Opcode Address (a) Instruction format Magnitude (b) Integer format Program counter (PC)= Address of instruction Instruction register (IR)- Instruction being executed Accumulator (AC) Temporary storage (c) Internal CPU registers -Load AC from memory Store AC to memory - Add to AC from memory (d) Partial list of opcodes Figure 8 Characteristics of a Hypothetical Machine Figure 9 illustrates a partial program execution, showing the relevant portions of memory and processor registers after the first instruction, 64H has…arrow_forwardComputer Sciencearrow_forward
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