Draw the mapping cache memory for this system and view the details of the connection between cache memory and main memory with this parameter ? Cache is divide into two memories (one for data and another for instruction) Cache size 16 bytes (8 for data 8 for instruction) Block line size 16bytes Main memory size is 16Mbytes and each byte addressing to 24 bit address Cache design 2-way set associative

Draw the mapping cache memory for this system and view the details of the connection between cache memory and main memory with this parameter ? Cache is divide into two memories (one for data and another for instruction) Cache size 16 bytes (8 for data 8 for instruction) Block line size 16bytes Main memory size is 16Mbytes and each byte addressing to 24 bit address Cache design 2-way set associative

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
Consider a system that has multiple processors where each processor has its own cache, but main memory is shared among all processors.q.) Which cache write policy would you use?
Consider an operating system using memory mapping on a page basis and using a single level page table. Assume that the necessary page table is always in memory. The system takes 200 ns to make a memory reference, how long does a paged memory reference take? Group of answer choices 400 ns (nanoseconds) 809.2 ms (microseconds) 200 ns (nanoseconds) 1638.4 ms (microseconds)
I am confused A memory system has a 32 KB byte-addressable main memory and a 1 KBcache where each block contains 16 bytes. Determine the format of the address in each of thecache organizations. In each case list the address fields and the width of each field.a) Direct-mapped cacheb) Fully-associative cachec) 4-way set-associative cache
please answer with proper explanation and step by step solution. Question As a simple model of a bus-based multiprocessor system without caching, suppose that one instruction in every four references memory, and that a memory reference occupies the bus for an entire instruction time. If the bus is busy, the requesting CPU is put into a FIFO queue. How much faster will a 64-CPU system run than a 1-CPU system? Note: Don't copy paste from online website.
Consider a system with 256Mbytes of main memory with page size of 4Kbytes. It has a logical address space of 26-bits. Answer the following questions. (Assume byte-addressable memory) (i) How many of the 26-bits of the logical address represent page# and how many bits represent the offset? (ii) How many entries are there in a conventional single-level page table for a process? (iii) How many entries are there in an inverted page table?
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Consider a system with 4GB of memory address space. Assuming a write-back policy and block size of 32 bytes, find the space overhead when it uses a (a) 64 KB direct mapped cache(b) fully associative cache (c) eight-way set-associative cache
Consider a computer with the following characteristics• total of 1Mbyte of main memory• word size of 1 byte• block size of 64 bytes• cache size of 128 Kbytes.a) How many bits should be reserved for tag, line, and word offsets for a direct-mapped cache.b) How many bits should be reserved for tag and word offset for a fully-associative cache.c) How many bits should be reserved for tag, cache set, and word offset for a 8-way set-associative cache.
Show work and type answer please. Suppose a computer using fully associate cache has 2G Bytes of main memory and a cache of 256 Blocks, where each cache Block has 8 Words, and the Word Size is 2 Bytes. a. How many blocks of main memory? b. What is the format of a memory address as seen by the cache? c. To which cache block will the memory reference 00001C4A in Hex?
a) A system implements a paged virtual address space for a process using a one-level page table.The maximum size of an address space of process is 16 megabytes.The page table for the running process includes the following entries:Page Number Frame Number 0 4 1 8 2 16 3 17 4 9 The page size is 1024 bytes and the maximum physical memory size of the machine is 2megabytes. Assuming two bits for protection and reference etc.1) How many bits are required for each page table entry?2) What is the maximum number of entries in a page table?3) How many bits are there in a virtual address?4) To which physical address will the virtual address 1524 translate to?