For a one-dimensional dynamic programming cache, a one-dimensional dynamic programming technique is necessary.

Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes.  a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?  b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache

Describe write-through and write-back cache modification as they are used in shared memory systems, and the advantages and disadvantages of both approaches.

I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?

In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.

Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?

It is important to make a distinction between caches that are fully associative and caches that are directly mapped.

A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.

Q10 In symmetric multiprocessor scheduling using private queues, when the scheduler running on a processor seeks to change its workload because it has no tasks to run, it performs a specific type of action called a Enter your answer here Q11 Consider the following pseudo-code implementation of a semaphore wait operation. void wait() { disable interrupts; sem value = sem value- 1; if ( sem value < 0) { block the calling process, adding it to sem_queue; schedule a process from the ready queue; enable interrupts; Is this code free of race conditions on a SMP? O Yes O No

If a dynamic programming technique's cache is one-dimensional, the dynamic programming method must be one-dimensional as well.Is this statement true or false?