initialized to 22. Suppose you executed the code below on a version of the pipeline from your textbook that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be?

initialized to 22. Suppose you executed the code below on a version of the pipeline from your textbook that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Th is exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath:add r5,r2,r1lw r3,4(r5)lw r2,0(r2)or r3,r5,r3sw r3,0(r5)> If there is no forwarding or hazard detection, insert nops to ensure correct execution.> Repeat above step, but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary values in your modifi ed code.> If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes?
Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?
Even when several processors are available, it is often a good idea to perform numerous operations in a pipeline on a single processor with pipelined parallelism.a. Justify your decision.b. If the computer has a shared-memory architecture, would the arguments you advanced in part a still be valid? Explain why you think that is or why you don't think that is.c. Do the arguments hold up with independent parallelism in part? (That is, are there any circumstances where, even if the operations are not pipelined and there are many processors available, performing many operations on the same processor is still a good idea?)
If you only use Stall, Forwarding and load ordering/code scheduling to overcome the data hazard howmany clock cycles you would need for executing above code sequence? Draw the datapath as well ascalculate the CPI. you will need to draw appropriate datapath showing the pipeline stages andhazard removal methods.
In 32-bit mode, aside from the stack pointer(ESP), what other register points to variables on the stack? Name at least four CPU status flags. Which flag is set when the result of an unsigned arithmetic operation is too large to fit into the destination? Which flag is set when the result of a signed arithmetic operation is either too large or too small to fit into the destination? (True/False): When a register operand size is 32 bits and the REX prefix is used, the R8D register is available for programs to use. Which flag is set when an arithmetic or logical operation generates a negative result? Which part of the CPU performs floating-point arithmetic? On a 32-bit processor, how many bits are contained in each floating-point data register? (True/False):The x86-64 instruction set is backward-compatible with the x86 instruction set. (True/False): In current 64-bit chip implementations, all 64 bits are used for addressing. (True/False):The Itanium…
(a) Which registers are used to access the stack ?(b) With each PUSH instruction, the stack pointer register SP is incremente or decremented by 2.(c) With each POP instruction, SP is incremented or decremented by 2.(d) List three possible logical addresses corresponding to physical address 143F0.(e) The ADD instruction can affect which bits of the flag register ?(f) The carry flag will be set to 1 in an 8-bit ADD if there is a carry out from bit . . .(g) CF will be set to 1 in a 16-bit ADD if there is a carry out from bit . . .
Describe the challenges associated with maintaining the correct order of instructions in an out-of-order pipeline. How does the reorder buffer (ROB) help address these challenges?
This question is on Computer Architecture. Translate the following arithmetic and logical expressions written in C programming language intoinstructions sequences written in MIPS Assembly language. You may assume that the values (orbase addresses) of the variables a, b, c, and d are in the general-purpose registers $s0, $s1,$s2, and $s3. 1. d[3] = a - b + c[7];2. c[5] = (a << 3) & (b >> 2);Here, <<, >>, and & indicate the bitwise left-shift, right-shift, and AND operations respectively.
For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)
Make a pipeline diagram of the code and insert NOP where needed. What kind of risks (pipeline hazards) are there in the diagram / table you did? At least how many cycles does the code need to be performed? while(a<10){ D[a] = b+a; a += 1; } The MIPS code below is equivalent to the C code above. The variables a and b are stored in registers $ s0 and $ s1 respectively. Loop: slti $t0, $s0, 10 beq $t0, $zero, exit sll $t1, $s0, 2 add $t1, $t1, $s2 add $t2, $s1, $s0 sw $t2, 0($t1) addi $s0, $s0, 1 j Loop exit:
Suppose that the execution time of a given program on a single processor is 9.5 ms. If you run this program on a system having 18 independent processors, you observe an overall speedup of 1.1. Using Amdahl’s Law, what must have been the fraction of the program that could be executed in parallel? (Express the answer in decimal form, i.e., if 50% of the program can be enhanced, enter 0.5. Round to three decimal places)
For the following code, explain what the register file and forwarding unit are doing during thefifth cycle of execution. If any comparisons are being made, mention them. Remember, usethe forwarding unit from class, not the book. LOOP:LDUR X1, [X6, #40]ADD X5, X5, X8ADD X6, X6, X8STUR X1, [X5, #20]CBZ X1, LOOP