Memory Write in the decimal values for each address below, and convert to binary: RAM16K minimum address (first address) = ( )10 [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] RAM16K maximum address (last address) = ( )10 [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] SCREEN Pointer address (start of screen memory map) = ( )10 [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Last possible address for screen memory map = ( )10 [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] KBD Pointer address = ( )10 [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] The A-instruction: symbolic and binary syntax Semantics: Set the A register to value Symbolic syntax: @value Where value is either: a non-negative decimal constant ≤32767 (=215-1) or a symbol referring to such a constant (later) Example: @21 Effect: sets the A register to 21 Binary syntax: Ovvvvvvvvvvvvvvvv For example: @21 (symbolic syntax- assembly code) 0000000000010101 (binary syntax- machine code) Symbolic syntax: dest = comp; jump Binary syntax: 1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 dest d1 d2 d3 effect: the value is stored in: The value is not stored 1 RAM[A] 10D register 0 1 1 RAM[A] and D register A register 101 1 1 0 comp c1 c2 c3 c4 c5 c6 0 101 010 null 1 -1 1 1 1 1 1 1 1 1 1 0 1 0 M D D 0 0 1 1 0 0 MD A M 1 1 0 0 0 0 A 1 ID 0 0 110 1 AM IA IA IM 1 1 0 0 0 1 AD 0 -D 001111 AMD 1 1 1 A -A -M D+1 A+1 M+1 D-1 1 1 0 0 1 1 01 1 1 1 1 1 10 11 1 001110 jump null A-1 M-1 110010 JGT JEQ D+A D+M D-A D-M 010011 JGE 0 1 1 A-D M-D JLT 100 D&A D&M ONE DIA D❘M 0 1 0 1 0 1 JLE a-0 a-1 JMP j1 j2 j3 A register and RAM[A] A register and D register A register, RAM[A], and D register effect: eno jump 001 if out > jump 0 1 0 if out 0 jump if out 20 jump if out < jump 101 if out 0 jump 110 if out se jump 1 1 1 Unconditional jump Recall the two Assembly Instructions, A and C: The A-instruction Syntax: @value The C-instruction Where value is either: a a non-negative decimal constant or dest comp; jump (both dest and jump are optional) where: aa symbol referring to such a constant (later) comp= Semantics: dest=null, M, D, MD, A, AM, AD, AMD ⚫Sets the A register to value ⚫Side effect: RAM[A] becomes the selected RAM register Example: @21 Effect: Sets the A register to 21 RAM[21] becomes the selected RAM register e, 1, -1, D, A, ID, IA, D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, DIA M, IM, -M, M+1, M-1, D+M, D-M, M-D, D&M, DIM. M refers to RAM[A] jump null, GT, JEQ, JGE, LT, JNE, JLE, JMP Semantics: Compute the value of comp Stores the result in dest; If the Boolean expression (comp jump 0) is true, jumps to execute the instruction stored in ROM[A]. if (comp jump 0) jump to execute the instruction in ROM[A]

A(n) __________ is a storage location implemented in the CPU.

Why is binary data representation and signaling the preferred method of computer hardware implementation?

How is an array stored in main memory? How is a linked list stored in main memory? What are their comparative advantages and disadvantages? Give examples of data that would be best stored as an array and as a linked list.

If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?

_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.

How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?

A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.

Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?