Problem 5 Write the entire VHDL code for a 64-bit synchronous counter that has a synchronous reset and an asynchronous preset. The preset value is 2048 and the reset value is all 0's. The 4 MSBS of the counter output also feeds a 4-1 mux. Show a schematic.

Draw a 4-input adder for single-bit values: that is, a set of logic gates with 4 input wires each representing a number between 0 and 1 and a multi-bit output z, composed of wires z0 through z... (where z0 is the low-order bit, z1 the next, etc., up to the number of wires needed for this task). The gates should ensure that z = the sum of all four inputs.

Solve number 2