Q7) Giving the following main memory address format for 8-way set associative cache: Tag=13, Set=13, Word%=6. Find the following: a. Size of main memory b. Size of cache memory c. Number of blocks in cache d. Number of bytes in each block e. If the cache access takes one and half clk cycle, and main memory takes two and half clk cycles, what is the effective memory cycle given miss rate 2% and clk rate 20MHZ.

Q7) Giving the following main memory address format for 8-way set associative cache: Tag=13, Set=13, Word%=6. Find the following: a. Size of main memory b. Size of cache memory c. Number of blocks in cache d. Number of bytes in each block e. If the cache access takes one and half clk cycle, and main memory takes two and half clk cycles, what is the effective memory cycle given miss rate 2% and clk rate 20MHZ.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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please sol Q1) Given a memory of 16k and a cache memory of 1024 bytes with block size 128 bytes. Thesystem uses Direct mapping.A- How many blocks available in both physical memory and cache memory B- How the address will be split to indicate tag, line (block no) and offsetC- Calculate the cache line number and offset in cache that will contain the content ofmemory address 230.
Assume you have a cache/memory system with the following characteristics: Size of a word: 4 bytes Size of a cache block: 4 words Size of cache: 16 words Associativity of the cache: 2-way Set Associative. Replacement Policy: LRU (Least Recently Used) How many sets are present in this cache? Assume that the following word addresses are accessed as read in the following order. In each case, say whether or not the corresponding access is a hit or a miss. If it is a miss, specify what kind of miss it is. Words accessed: 4, 3, 6, 8, 1, 24, 16, 19, 20, 19, 1. What is the miss rate for this cache and this pattern of word accesses? Draw a figure showing the final state of the cache.
7. Information can be retrieved fastest from: A) hard disk. B) magnetic tape. C) optical disk. D) USB flash drive. 8. Cache mapping is necessary because: A) the address generated by the CPU must be converted to a cache location. B) cache is so small that its use requires a map. C) cache is larger than main memory and mapping allows us to store multiple copies of each piece of data from main memory. D) None of these is correct. 9. The offset field of a main memory address is used to determine: A) if the cache entry is valid. B) if the cache entry is the desired block. C) the location of the desired data in the cache block. D) None of these is correct. 10. Cache replacement policies are necessary: A) to determine which cache mapping policy to use. B) to determine which block in cache should be the victim block. C) to decide where to put blocks when cache is empty. D) All of these are correct. 11. Cache memory is effective because: A) it is very inexpensive. B) it is very large. C) it is…
Below is a list of 32-bit memory address references, given as memory addresses. 12, 720, 172, 8, 764, 352, 760, 56, 724, 176, 744You would like to access a cache with the given memory addresses. The size of cache is 23 = 8-blocks. Your task is to: (1) find out the binary address, (2) fill out the tag and index for each memory address and (3) indicate whether the access is hit or miss in the following table:
Media applications that play audio or video files are part of a class of workloads called “streaming” workloads; i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KiB working set sequentially with the following address stream: 0, 2, 4, 6, 8, 10, 12, 14, 16, ... Assume a 64 KiB direct-mapped cache with a 32-byte block. What is the miss rate for the address stream above? How is this miss rate sensitive to the size of the cache or the working set? How would you categorize the misses this workload is experiencing, based on the 3C model? Re-compute the miss rate when the cache block size is 16 bytes, 64 bytes, and 128 bytes. What kind of locality is this workload exploiting?
6 Recall that we have two write policies and two write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 6.1 Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory. 6.2 Describe the procedure of handling an L1 write-miss, considering the components involved and the possibility of replacing a dirty block. 6.3 For a multilevel exclusive cache con guration (a block can only reside in one of the L1 and L2 caches), describe the procedures of handling an L1 write-miss and an L1 read-miss, considering the components involved and the possibility of replacing a dirty block.
QUESTION 22 Assume a cache has 16 entries. How many index bits are needed to address the cache? a. 2 b. 4 c. 5 d. 16 QUESTION 23 Which of the following statements about cache write policy is NOT true? a. A dirty bit is used to implement a write back approach. b. A cache entry with dirty bit = 1 means the data inside is safe to be replaced. c. A write back approach is not suitable for multiple processors accessing the same memory. d. A write back approach is typically faster than a write through approach. QUESTION 25 Which of the following statements is true of normalized scientific notation? a. 3.06 x 10^3 is in decimal normalized scientific notation b. 0.30 x 10^3 is in decimal normalized scientific notation c. 0.11 x 10^5 is in binary normalized scientific notation d. 10.01 x 10^5 is in binary normalized scientific notation
Assume you have a cache/memory system with the following characteristics: Size of a word: 8 bytes Size of a cache block: 32 words Size of the cache: 1024 words How many bits are in the tag if the cache is: direct-mapped, 2-way set associative, 4-way set associative, fully associative? Why?
Q.A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into cache.) Assume that a request is always started in parallel to both cache and to main memory (so if it is not found in cache, we do not have to add this cache search time to the memory access). If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty.Q.) Compute the hit ratio for a program that loops four times from addresses 0x0 to 0x43 in memory.
Q.A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into cache.) Assume that a request is always started in parallel to both cache and to main memory (so if it is not found in cache, we do not have to add this cache search time to the memory access). If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty.Q.) Show the main memory address format, which allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.
The following blocks are referenced by the CPU and to be fetched from the RAM to the cache sequentially: (ij k L L jmj n L mj m L k sįPi o k) Assume that the cache set is empty and all the above blocks can be inserted into the set. Use the LRU algorithm to fill in the following table that describes the status of the cache locations for each called block .
Please help me in this question: 19/ A larger block size in a cache will __________ . a. reduce the miss rate due to spatial locality b. increase the miss rate as data is typically scattered c. decrease the size of the swap memory d. ensure a smaller miss penalty Thank you!