A two-way set associative cache memory uses blocks of four words. The cache can accommodate a total of 512 words from main memory. The main memory size is 4096 x 16 bits. a) Formulate all information required to construct the cache memory. How many bits are there in TAG, BLOCK (row) and WORD (column) fields? b) If this writeback data cache is using LRU replacement policy, trace the execution of the following references by filling in the table. ( all addresses are given HEX form) Reference Tag Set Way Hit/Miss Writeback 1 Store 714 2 Store 119 3 Load A16 4 Load 21B 5 Store 714 6 Store 815 7 Load 318 8 Store 219 Store 116 10 Load A17

A two-way set associative cache memory uses blocks of four words. The cache can accommodate a total of 512 words from main memory. The main memory size is 4096 x 16 bits. a) Formulate all information required to construct the cache memory. How many bits are there in TAG, BLOCK (row) and WORD (column) fields? b) If this writeback data cache is using LRU replacement policy, trace the execution of the following references by filling in the table. ( all addresses are given HEX form) Reference Tag Set Way Hit/Miss Writeback 1 Store 714 2 Store 119 3 Load A16 4 Load 21B 5 Store 714 6 Store 815 7 Load 318 8 Store 219 Store 116 10 Load A17

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way setassociative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful todraw a table.Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0.a– Assuming an LRU replacement policy, how many hits does this address sequenceexhibit? Please show the status of the cache after each address is accessed.b – Assuming an MRU (most recently used) replacement policy, how many hits doesthis address sequence exhibit? Please show the status of the cache after each address is accessed.
Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction…
A two-way set associative cache memory uses blocks of four words. The cache can accommodate a total of 512 words from main memory. The main memory size is 4096 x 16 bits. Formulate all information required to construct the cache memory. How many bits are there in TAG, BLOCK (row) and WORD (column) fields? If this writeback data cache is using LRU replacement policy, trace the execution of the following references by filling in the table. ( all addresses are given HEX form)
In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.” Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0. 5.1 – Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed. 5.2 – Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.
In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 16, 0 Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Simulate a random replacement policy by flipping a coin. For example, “heads” means to evict the fi rst block in a set and “tails” means to evict the second block in a set. How many hits does this address sequence exhibit? Which address should be evicted at each replacement to maximize the number of hits? How many hits does this address sequence exhibit if you follow this “optimal” policy? Describe why it is diffi cult to implement a cache…
In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.” Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0. 1. Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed. 2. Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.
In this exercise, we will look at the diff erent ways capacity aff ects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. Th e following table shows data for L1 caches attached to each of two processors, P1 and P2. L1 Size L1 Miss Rate L1 Hit Time P1 2 KiB 8.0% 0.66 ns P2 4 KiB 6.0% 0.90 ns Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? What is the Average Memory Access Time for P1 and P2? Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
A computer uses a set - associative cache with 8 - blocks per set . 1. How many bits will be used for the counter to apply the ( LRU algorithm ) ? Explain your answer . 2. The following blocks are referenced by the CPU and to be fetched from the RAM to the cache sequentially : ( i j k LL jmjnim jm LkSj Pi o k ) Assume that the cache set is empty and all the above blocks can be inserted into the set . Use the LRU algorithm to fill in the following table that describes the status of the cache locations for each called block .
A Direct mapped cache has a capacity of 16-word cache and a block size of 4 words. Consider the following repeating sequence of lw addresses (given in hexadecimal): 74 A0 78 38C AC 84 88 8C 7C 34 38 13C 388 18C Determine the effective miss rate if the sequence is input to the following caches, ignoring startup effects.
A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
A two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.
There is a cache with 8 blocks, find the number of misses for each cache organization (Direct-mapped, 2-way associative, 4-way associative) given the following sequence of block addresses: 10110, 11110, 10111, 10110, 11110, 10111 11110,10110,00011,10000,10010,10000