Question 2 A Verilog module named "Sample" is declared as below: module Sample(clock, reset, w, Q); where input and output ports are defined as: input clock, reset, w; localparam m=8; output reg [m-1:0] Q; Q[O] is the right most bit and Q[m-1] is the left-most bit in the configuration. Input w provides the serial input to the circuit. Which of the following correctly implements a left-shift register? integer k; always@(posedge clock) begin if (reset) Q<=0; else begin for (k=m-1; k>=1; k=k-1) Q[K]<=Q[k-1]; Q[m-1]<=w; end end integer k; always@(posedge clock) begin if (reset) Q<=0; else begin for (k=1; k<=m-1; k=k+1) Q[k]=Q[k-1]; Q[0]=w; end end integer k; always@(posedge clock) begin if (reset) Q<=0; else begin for (k=m-1; k>=1; k=k-1) Q[K]<=Q[K-1]; Q[0]<=w; end end integer k; always@(posedge clock) begin if (reset) Q<=0; else begin for (k=1; k<=m-1; k=k+1) Q[K-1]<=Q[k]; Q[m-1]<=w; end end

Write a function in MIPS Assembly Language that computes the next state of a linear feedback shift register (LFSR) given the current state of the LFSR. The LFSR should satisfy the taps given by the following polynomial: x^15 + x^14 +1 Your function should take the state as a 32-bit input parameter and return a 32-bit output value. Your main program for the function should call your LFSR function for the following input states and print the output state: 0x00000001 0xdeadbeef 0x200214c8 0x00000000

assembly programming

Q2. [Structural Verilog] Design a 2-bit subtractor unit. Inputs are A and B, and output is S, 2-bits each. As a sub-module you can call the Full Adder module (E Assume this is given to you as library) which takes in 3 inputs (X, Y and Z) and produces 2 outputs (F, C). Write structural HDL